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| motorola mc68en302 reference manual iii mc68en302 integrated multiprotocol processor with ethernet reference manual microprocessors and memory
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iv mc68en302 reference manual motorola motorola mc68en302 reference manual v preface the complete documentation package for the mc68en302 consists of mc68en302rm/ad, the mc68en302 integrated multiprotocol processor with ethernet, mc68302um/ad, the mc68302 integrated multiprotocol processor, mc68en302/d, the mc68en302 integrated multiprotocol processor with ethernet product brief ; and m68000pm/ad, the m68000 pro- grammer? reference manual . the mc68en302 integrated multiprotocol processor with ethernet user? manual describes the programming, capabilities, registers, and operation of the mc68en302 that differs from the mc68302; the mc68302 integrated multiprotocol processor describes the original mc68302, the mc68en302 integrated multiprotocol processor with ethernet product brief provides a brief description of the mc68en302 capabilities; and the m68000 programmer? reference manual describes programming and the instruction set for the imp processor. this user? manual is organized as follows: section 1 introduction section 2 module bus controller section 3 dram control module (dcm) section 4 ethernet controller section 5 signal description section 6 applications section 7 ieee 1149 test access port (tap) section 8 electrical specifications section 9 ordering information and mechanical data applications and technical information for questions or comments pertaining to technical information, questions, and applications, please contact one of the following sales offices nearest you. vi mc68en302 reference manual motorola sales offices united states field applications engineering available through all sales office alabama , huntsville (205) 464-6800 arizona , tempe (602) 897-5056 california , agoura hills (818) 706-1929 california , los angeles (310) 417-8848 california , irvine (714) 753-7360 california , rosevllle (916) 922-7152 california , san diego (619) 541-2163 california , sunnyvale (408) 749-0510 colorado , colorado springs (719) 599-7497 colorado , denver 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(310) 594-4631 motorola mc68en302 reference manual vii documentation feedback fax 512-891-8593?ocumentation comments only (no technical questions please) http: / / www.mot.com/hpesd/docs_survey.html?ocumentation feedback only the motorola technical communications department welcomes your suggestions for improving our documentation and encourages you to complete the documentation feedback form at the world wide web address listed above. in return for your efforts, you will receive a small token of our appreciation. your help helps us measure how well we are serving your information requirements. we also provide a fax number for you to submit any questions or comments about this document or how to order other documents. please provide the part number and revision number (located in upper right-hand corner of the cover) and the title of the document. when referring to items in the manual, please reference by the page number, paragraph number, figure number, table number, and line number if needed. please do not fax technical questions to this number. when sending a fax, please provide your name, company, fax number, and phone number including area code. for internet access: telnet: pirs.aus.sps.mot.com (login: pirs) www: http: / / pirs.aus.sps.mot.com/aesop/hmpg.html query by email: aesop_query@pirs.aus.sps.mot.com (type help in text body.) for dial-up: phone: +1-512-891-3650 phone (us or canada): 1-800-843-3451 connection settings: n/8/1/f data rate: < 14,400 bps terminal emulation: vt100 login: pirs for aesop questions: fax: +1-512-891-8775 email: aesop_sysop@pirs.aus.sps.mot.com for hotline questions: fax (us or canada): 1-800-248-8567 email: aesop_support@pirs.aus.sps.mot.com motorola mc68en302 user? manual vii table of contents paragraph title page number number section 1 introduction 1.1 feature list ............................................................................................. 1-1 1.2 block diagram......................................................................................... 1-2 1.3 memory map ........................................................................................... 1-2 1.3.1 module controller base address register (mobar) address ($ee) ..... 1-3 1.4 register overview................................................................................... 1-3 section 2 mc68en302 module bus controller 2.1 introduction ............................................................................................. 2-1 2.2 top level memory map .......................................................................... 2-2 2.3 mbc registers ........................................................................................ 2-2 2.4 module bus control (mbctl) ................................................................. 2-2 2.5 interrupt extension register (ier) .......................................................... 2-3 2.6 chip select extension registers (cser3?ser0) ............................... 2-4 2.7 parity control and status register (pcsr) ............................................ 2-6 2.8 bus interface ........................................................................................... 2-7 2.8.1 bus arbitration......................................................................................... 2-7 2.9 dynamic bus sizing ................................................................................ 2-7 2.9.1 bus cycle timing .................................................................................... 2-9 2.9.2 bus error handling................................................................................ 2-10 2.9.3 retry handling ...................................................................................... 2-11 2.10 parity logic ........................................................................................... 2-11 2.10.1 parity generation .................................................................................. 2-11 2.10.2 parity checking ..................................................................................... 2-11 2.10.3 parity error reporting ........................................................................... 2-11 2.10.4 parity pin enable................................................................................... 2-12 2.11 interrupt support ................................................................................... 2-12 section 3 mc68en302 dram control module 3.1 introduction ............................................................................................ 3-1 3.2 memory map .......................................................................................... 3-1 3.3 dram configuration register (dcr)..................................................... 3-1 3.4 dram refresh register (drfrsh) ...................................................... 3-2 3.5 dram base address register (dba1-dba0) ....................................... 3-3 3.6 dram control module operation .......................................................... 3-3 3.6.1 reset operation ..................................................................................... 3-3 table of contents paragraph title page number number viii mc68en302 user? manual motorola 3.6.2 read and write cycle operation ............................................................ 3-4 3.7 refresh operation................................................................................... 3-5 3.8 dram controller i/o ............................................................................... 3-6 3.8.1 control signal pins ................................................................................. 3-6 3.8.2 column address strobes (cas1?as0)................................................ 3-6 3.8.3 row address strobes (ras1?as0) ..................................................... 3-6 3.8.4 dram read/write (dramrw) .............................................................. 3-6 3.8.5 address mux (amux) ............................................................................. 3-7 3.8.6 parity (parity1?arity0) ................................................................... 3-7 3.8.7 muxing scheme ...................................................................................... 3-7 section 4 ethernet controller 4.1 register description.................................................................................4-2 4.1.1 ethernet control register (ecntrl).......................................................4-3 4.1.2 ethernet dma configuration status register (edma).............................4-3 4.1.3 ethernet maximum receive buffer length (emrblr)............................4-5 4.1.4 interrupt vector register (ivec) ..............................................................4-6 4.1.5 interrupt event register (intr_event) .................................................4-6 4.1.6 interrupt mask register (intr_mask)....................................................4-8 4.1.7 ethernet configuration (ecnfig) ............................................................4-9 4.1.8 ethernet test (ether_test)...............................................................4-10 4.1.9 ar control register (ar_cntrl).........................................................4-11 4.2 ethernet buffer descriptors....................................................................4-12 4.2.1 ethernet receive buffer descriptor (rx bd)..........................................4-13 4.2.2 ethernet transmit buffer descriptor ......................................................4-16 4.3 dma and buffer descriptor logic ..........................................................4-18 4.3.1 buffer descriptor logic ..........................................................................4-18 4.3.2 dma logic .............................................................................................4-19 4.4 transmit and receive fifos .................................................................4-19 4.4.1 transmit fifo........................................................................................4-19 4.4.2 receive fifo.........................................................................................4-20 4.5 ethernet protocol logic..........................................................................4-20 4.5.1 ethernet transmit ..................................................................................4-20 4.5.2 ethernet receive ...................................................................................4-21 4.5.3 ethernet loopback.................................................................................4-22 4.6 ethernet ar (address recognition).......................................................4-22 4.6.1 buffer descriptor modification................................................................4-23 4.6.2 writing addresses into tables ...............................................................4-25 4.6.3 reading addresses from tables............................................................4-27 section 5 signal descriptions 5.1 pin/signal combinations..........................................................................5-1 5.2 mc68en302/mc68302 common signals ...............................................5-4 5.3 mc68302 signals removed or redefined...............................................5-5 table of contents paragraph title page number number motorola mc68en302 user? manual ix 5.3.1 rmc/iout1............................................................................................. 5-5 5.3.2 iac .......................................................................................................... 5-6 5.3.3 bclr....................................................................................................... 5-6 5.3.4 frz ......................................................................................................... 5-6 5.3.5 busw...................................................................................................... 5-6 5.3.6 discpu................................................................................................... 5-6 5.4 mc68en302 new signals muxed with existing mc68302 signals......... 5-6 5.4.1 amux - dram address mux .................................................................. 5-7 5.4.2 ras0 - dram row address select, bit zero ......................................... 5-7 5.4.3 ras1 - dram row address select bit 1................................................ 5-7 5.4.4 cas0 - dram column address select bit 0 .......................................... 5-7 5.4.5 cas1- dram column address select bit 1 ........................................... 5-7 5.4.6 dramrw- dram read/write ................................................................ 5-7 5.4.7 a0 ............................................................................................................ 5-8 5.4.8 wel- write enable for byte 1 (bit 7?it 0).............................................. 5-8 5.4.9 weh - write enable for byte 0 (bit 15?it 8) .......................................... 5-8 5.4.10 oe - output enable ................................................................................. 5-8 5.5 mc68en302 only pin/signals ................................................................ 5-8 5.5.1 gnd ........................................................................................................ 5-8 5.5.2 trst - jtag reset signal ..................................................................... 5-8 5.5.3 tms - jtag test mode select ............................................................... 5-9 5.5.4 tdo - jtag test data out ..................................................................... 5-9 5.5.5 tdi - jtag test data in.......................................................................... 5-9 5.5.6 tck- jtag clock.................................................................................... 5-9 5.5.7 gnd ........................................................................................................ 5-9 5.5.8 tena....................................................................................................... 5-9 5.5.9 tclk ....................................................................................................... 5-9 5.5.10 rclk....................................................................................................... 5-9 5.5.11 rx ........................................................................................................... 5-9 5.5.12 rena ...................................................................................................... 5-9 5.5.13 clsn....................................................................................................... 5-9 5.5.14 parity0/discpu................................................................................... 5-9 5.5.15 parity1/busw.................................................................................... 5-10 5.5.16 paritye/threestate ...................................................................... 5-10 5.6 dram controller i/o ............................................................................. 5-10 5.6.1 control signal pins................................................................................ 5-10 5.6.2 column address strobes (cas1?as0) .............................................. 5-10 5.6.3 row address strobes (ras1?as0) ................................................... 5-10 5.6.4 dram read/write (dramrw)............................................................. 5-10 5.6.5 address mux (amux)............................................................................ 5-11 5.6.6 parity (parity1?arity0).................................................................. 5-11 5.6.7 muxing scheme..................................................................................... 5-11 table of contents paragraph title page number number x mc68en302 user? manual motorola section 6 applications 6.1 bringing the mc68en302 out of reset ...................................................6-1 6.2 moving a quicc ethernet driver to a 68en302 ethernet driver ............6-3 6.2.1 c_pres, c_mask:.................................................................................6-4 6.2.2 crcec: ...................................................................................................6-4 6.2.3 alec:.......................................................................................................6-4 6.2.4 disfc: .....................................................................................................6-4 6.2.5 pads: ......................................................................................................6-4 6.2.6 ret_lim:.................................................................................................6-4 6.2.7 ret_cnt: .................................................................................................6-5 6.2.8 mflr: ......................................................................................................6-5 6.2.9 minflr:...................................................................................................6-5 6.2.10 maxd1, maxd2: .....................................................................................6-5 6.2.11 max_b: ....................................................................................................6-5 6.2.12 gaddr1-4 / paddr_hml / iaddr1-4: .................................................6-5 6.2.13 p_per: ....................................................................................................6-5 6.2.14 rfbd_ptr/tfbd_ptr/tlbd_ptr: ...............................................................6-5 6.2.15 tx_len:.....................................................................................................6-5 6.2.16 boff_cnt: .............................................................................................6-6 6.2.17 taddr_h/m/l: ........................................................................................6-6 6.2.18 gsmr (quicc section 7.10.2) ...............................................................6-6 section 7 ieee 1149.1 (jtag) test access port 7.1 overview ..................................................................................................7-1 7.2 tap controller .........................................................................................7-2 7.3 boundary scan register ..........................................................................7-3 7.4 instruction register ................................................................................7-12 7.4.1 extest .................................................................................................7-13 7.4.2 sample/preload ..............................................................................7-13 7.4.3 bypass.................................................................................................7-13 7.4.4 clamp...................................................................................................7-14 7.4.5 hi-z ........................................................................................................7-14 7.5 mc68en302 restrictions.......................................................................7-14 7.6 non-scan chain operation....................................................................7-14 section 8 mc68en302 electrical characteristics 8.1 power dissipation ....................................................................................8-1 8.2 changes to existing mc68302 timing specs..........................................8-1 8.3 dram interface timing............................................................................8-2 8.4 ethernet timing........................................................................................8-5 8.5 jtag interface timing .............................................................................8-7 8.6 oe, wel, weh timing............................................................................8-9 8.6.1 oe timing ................................................................................................8-9 table of contents paragraph title page number number motorola mc68en302 user? manual xi 8.6.2 wel, weh timing .................................................................................. 8-9 section 9 ordering and mechanical information 9.1 pin assignment ....................................................................................... 9-1 9.1.1 pin grid array (pga)............................................................................... 9-2 9.1.2 144 thin quad flat pack (tqfp)............................................................ 9-3 9.2 package dimensions............................................................................... 9-4 9.2.1 pin grid array (pga)............................................................................... 9-4 9.2.2 144 thin quad flat pack (tqfp)............................................................ 9-5 9.3 standard ordering information................................................................ 9-6 xii mc68en302 user? manual motorola list of figures figure title page number number figure 1-1. mc68en302 block diagram ................................................................... 1-2 figure 2-1. top level bus structure.......................................................................... 2-1 figure 2-2. 8-bit external to 16-bit internal read ...................................................... 2-8 figure 2-3. 16-bit internal to 8-bit external write....................................................... 2-8 figure 2-4. word read with 3-clock 8-bit accesses................................................. 2-9 figure 2-5. word write with 3-clock 8-bit accesses................................................. 2-9 figure 2-6. fast cycle word read with ? wait state ............................................ 2-10 figure 2-7. fast cycle word write with -1 wait state ............................................. 2-10 figure 2-8. external and internal interrupt prioritization.......................................... 2-13 figure 3-1. consecutive four-clock accesses ........................................................ 3-4 figure 3-2. five-clock accesses with three-clock precharge ................................ 3-5 figure 3-3. precharge with dram access active ................................................... 3-6 figure 4-1. ethernet controller block diagram.......................................................... 4-2 figure 4-2. ethernet receive buffer d.0escriptor (rx bd)...................................... 4-13 figure 4-3. ethernet transmit buffer descriptor (tx bd) ........................................ 4-16 figure 4-4. ethernet address recognition flowchart.............................................. 4-25 figure 4-5. ar memory map - perfect match mode................................................ 4-26 figure 4-6. ar memory map - hash mode.............................................................. 4-27 figure 7-1. test logic block diagram ....................................................................... 7-2 figure 7-2. tap controller state machine................................................................. 7-3 figure 7-3. output latch cell (iocell)......................................................................... 7-8 figure 7-4. input pin cell (iscell) ............................................................................... 7-8 figure 7-5. control cell (dicell).................................................................................. 7-9 figure 7-6. bidirectional cell (bicell).......................................................................... 7-9 figure 7-7. output enable cell (encell) ................................................................... 7-10 figure 7-8. output enable cell (encello) ................................................................. 7-10 figure 7-9. output enable cell (clko_encell)........................................................... 7-11 figure 7-10. general arrangement for bidirectional pins.......................................... 7-12 figure 7-11. bypass register .................................................................................... 7-13 figure 8-1. dram read cycle .................................................................................. 8-3 figure 8-2. dram write cycle .................................................................................. 8-4 figure 8-3. dram refresh ........................................................................................ 8-5 figure 8-4. ethernet collision timing ........................................................................ 8-6 figure 8-5. ethernet receive timing......................................................................... 8-6 figure 8-6. ethernet transmit timing........................................................................ 8-6 figure 8-7. test clock input timing diagram............................................................ 8-7 figure 8-8. trst timing diagram ............................................................................ 8-7 figure 8-9. boundary scan (jtag) timing diagram................................................. 8-8 figure 8-10. test access port timing diagram........................................................... 8-8 motorola mc68en302 user? manual xiii list of tables table title page number number table 1-1. mc68en302 additional registers.............................................................1-4 table 2-1. high level memory map of mbc and mb modules ..................................2-2 table 2-2. module bus controller register set ..........................................................2-2 table 2-3. pin muxing operation................................................................................2-3 table 2-4. dt bit encoding ........................................................................................2-5 table 2-5. parity pin enable operation ....................................................................2-12 table 3-1. dram controller registers ...................................................................... 3-1 table 3-2. precharge bit encodings.......................................................................... 3-2 table 3-3. wait state bit encodings.......................................................................... 3-2 table 3-4. address muxing scheme ......................................................................... 3-7 table 4-1. ethernet controller memory map ..............................................................4-2 table 4-2. bd ram address ranges.......................................................................4-18 table 4-3. unicast address processing ...................................................................4-24 table 4-4. broadcast and multicast address processing .........................................4-24 table 5-1. mc68en302 144-tqfp pin/signal definition...........................................5-1 table 5-2. pin muxing control ....................................................................................5-6 table 5-3. address muxing scheme ........................................................................5-11 table 7-1. boundary scan control bits ......................................................................7-4 table 7-2. boundary scan bit definition.....................................................................7-6 table 7-3. instruction decoding................................................................................7-12 table 8-1. dram interface timing .............................................................................8-2 table 8-2. ethernet timing .........................................................................................8-5 table of contents paragraph title page number number xiv mc68en302 user? manual motorola motorola mc68en302 reference manual 1-1 section 1 introduction the mc68en302 is a multiprotocol integrated communications controller based on the mc68302. the original mc68302 provided multiple wan and isdn support with three serial communcations channels, glueless memory control for sram and eprom and various system integration features. the mc68en302 builds upon the success of the mc68302 by adding an ethernet controller which is completely independent of the three on-board serial channels as well as a dram control and a jtag interface. no communications related features of the original 302 are lost when using either the ethernet controller or the dram controller of the mc68en302. the ethernet controller provides a 16-bit interface and provides complete ieee 802.3 compatibility. the programming model for the ethernet controller is based on the standard mc68302 programming model. buffer descriptors for the ethernet controller are compatible wiith the buffer descriptors used by the mc68360 quicc ethernet controller. the dram controller is based upon other 300 family memory controllers with specific enhancements provided for supporting parity and external bus masters. the jtag interface is the standard ieee1149.1 test interface. 1.1 feature list the following mc68en302 features are in addition to the mc68302 feature list: full complement of existing three scc? plus ethernet channel ethernet channel fully compliant with ieee 802.3 mac specification. supports data rates up to 10 mbps. supports the mc68302 style programming model. bus bandwidth requirements reduced through 128 on-chip buffer descriptors. independant 128 byte transmit and receive fifo?. 64 entry cam for address recognition. ethernet collision results in retransmission from tx fifo (no external bus access). runt frames automatically cause rx fifo to flush internally. interfaces to mc68160 for 10base-t or aui connection. dynamic bus sizing glueless rom and sram interface dram controller glueless dram interface for internal bus master introduction 1-2 mc68en302 reference manual motorola amux signal provided for external bus master use parity generation/checking on a per byte basis fully ieee 1149.1 jtag compliant 144 tqfp package 1.2 block diagram the mc68en302 adds functionality to the pre-existing mc68302 by providing additional blocks external to the mc68302 which arbitrate for use of the 68000 bus for access to off- chip resources such as memory or other peripheral devices. this modular approach is shown in figure . figure 1-1. mc68en302 block diagram 1.3 memory map the mc68en302 memory map does not change the mc68302 memory map, but rather adds a new 4k module block. this is in addition to the 4k module block of the mc68302. because of the additional register block, there are two base address registers to program mc68000 microcoded communications controller (risc) interrupt controller 1 general- purpose dma channel 3 timers and additional features 6 dma channels 1152 bytes dual-port ram 3 serial channels other serial channels mc68302 68000 system bus peripheral bus dram controller ethernet controller mc68en302 jtag ieee 1149.1 module bus controller introduction motorola mc68en302 reference manual 1-3 in the mc68en302. the bar register is identical to the mc68302 bar, and the module controller base address register is specific to the mc68en302. 1.3.1 module controller base address register (mobar) address ($ee) the module controller base address register (mobar) sets the base address for the mc68en302 registers which are in addition to the register set of the mc68302. the mobar is located at address $0ee and its configuration and operation match the existing mc68302 bar. the value of mobar after reset defaults to $bffe which places the module controller block directly below the mc68302 block. the mc68en302 must be in supervisor mode for mobar to be written with a new value. fc2?c0?unction code 2?unction code 0 fc2-0 sets the address space of the 4 kbyte module controller block. depending on the value of the cfc bits, the mc68en302 address compare logic uses these bits to cause an address match within its address space.do not assign fc2-0 to the m68000 interrupt acknowledge space (fc2-0 = 111b). cfc?ompare function code when cleared, the fc bits in the mobar are ignored and accesses to the module controller block occur without comparing the fc bits. when set, the address space compare logic uses the fc bits in mobar to detect address matches. moba?odule controller base address. the high address field is contained in bits 11-0 of the mobar and sets the starting address of the module controller block. 1.4 register overview the control and status registers for the ethernet controller are all 16 bits with an address range of moba+$000 to moba+$fff. the mc68en302 registers in addition to the 302 register set are shown in table 1-1. note that even though the entire 302 register set is provided, special care must be taken when initializing the pre-existing 302 registers so there are no contention or compatibility issues during internal arbitration. the registers that require particular attention are: ?r gimr scr. also, notice that dtack is not returned for accesses to unimplemented csrs in the moba address space. 1514131211109876543210 fc2 fc2 fc0 cfc ba23 ba22 ba21 ba20 ba19 ba18 ba17 ba16 ba15 ba14 ba13 ba12 introduction 1-4 mc68en302 reference manual motorola table 1-1. mc68en302 additional registers address name mnemonic type moba + 000 module bus control mbc read/write moba + 002 interrupt extension register ier read/write moba + 004 chip select 0 extension register cser0 read/write moba + 006 chip select 1 extension register cser1 read/write moba + 008 chip select 2 extension register cser2 read/write moba + 00a chip select 3 extension register cser3 read/write moba + 00c parity control & status register pcsr read/write moba + 010 dram configuration register dcr read/write moba + 012 dram refresh register drfrsh read/write moba + 014 dram bank 0 base address register dba0 read/write moba + 016 dram bank 1 base address register dba1 read/write moba + 800 ethernet control register ecntrl read/write moba + 802 ethernet dma configuration register edma read/write moba + 804 maximum receive buffer length emrblr read/write moba + 806 interrupt vector register intr_vect read/write moba + 808 interrupt event intr_event read/write moba + 80a interrupt mask register intr_mask read/write moba + 80c ethernet configuration ecnfig read/write moba + 80e ethernet test register ether_test read/write moba + 810 address recognition control register ar_cntrl read/write moba + a00 moba + bff cam entry table cet read/write moba + c00 moba + fff buffer descriptors table ebd read/write motorola mc68en302 reference manual 2-1 section 2 mc68en302 module bus controller 2.1 introduction the model of the mc68en302 is such that the internal 302 functions are unaffected by the addition of an ethernet controller and the dram controller. the 302 core sees that it must arbitrate with other bus masters for access to the ?xternal?bus. in the mc68en302, the module bus controller provides the arbitration between the 302 core and the other modules (ethernet and dram) for access to the bus external to the mc68en302. the functions provided by the module bus controller (mbc) are as follows: interfaces between internal 68000 bus and the module bus. performs dynamic bus sizing utilizing the chip select logic of the internal 68302. provides interrupt handling for module bus modules. performs bus arbitration between external sources, the module bus, and the 68302 core. figure 2-1. top level bus structure mc68302 module bus controller modules module bus 68000 bus p a d s internal 68000 bus external 302 bus internal b u f f e r s mc68en302 module bus controller 2-2 mc68en302 reference manual motorola 2.2 top level memory map a top level diagram of register allocation for the modules in the mc68en302 is shown in table 2-1. a description of the dram control registers and the ethernet controller registers are contained in the description of those modules. table 2-1. high level memory map of mbc and mb modules 2.3 mbc registers a memory map of the mbc control registers is shown in table 2-2. 2.4 module bus control (mbctl) the module bus control register (mbctl) provides the user control over the system level functionality of the mbc. this register defaults to $0x5000 upon hardware reset. bce?us clear enable. this bit controls the way in which the mbc responds to the bus clear function inside the mc68en302. if bce is zero, the mbc ignores the bus clear (bclr ) signal giving the dram and ethernet modules priority over the 302 core. if this bit table 2-2. module bus controller register set address register name mnemonic moba + 000 module bus control register mbctl moba + 002 interrupt extension register ier moba + 004 chip select 0 extension register cser0 moba + 006 chip select 1 extension register cser1 moba + 008 chip select 2 extension register cser2 moba + 00a chip select 3 extension register cser3 moba + 00c parity control & status register pcsr 1514131211109876543210 bce mfc2 mfc1 mfc0 bb ppe pm9 pm8 pm7 pm6 pm5 pm4 pm3 pm2 pm1 pm0 moba + 000 moba + 00d moba + 010 moba + 019 moba + 800 moba + fff mbc registers dram controller registers ethernet controller registers address block mc68en302 module bus controller motorola mc68en302 reference manual 2-3 is set, the mbc relinquishes the bus when it detects bclr, allowing the internal 302 core priority over the dram and ethernet controllers. mfc?odule function code (mfc2-mc0). these bits determine the function code put out when the ethernet dma machine is active. bb?us error byte. this status bit (read-only) is the state of address 0 upon the last generated bus error. this information is useful when performing exception processing to determine the cause of bus errors generated when the 8-bit dynamic bus sizing option is used with the chip selects. ppe?arity pin enable. this bit, if set, enables parity on the appropriate pins. the parity signals are muxed on three mc68en302 configuration pins which are sampled at hard reset to determine device operation. once out of reset, the parity function may be enabled by the ppe bit. see 2.10.4 parity pin enable for more details. pm?in muxes pm9?m0. depending upon the setting of these bits, the mc68en302 is able to provide some enhancements over the 68302. because many of these enhancements are with existing 68302 pins, the enhancements are provided as programmable options. table 2-3 shows the effect of the pm bits. all pm bits are cleared at hardware reset. 2.5 interrupt extension register (ier) this register replaces the mod, et7, et6, and et1 bits in the pre-existing 302 gimr (global interrupt mode register) requiring that when writing to the internal 302 core gimr, the corresponding bits must be written as a zero.this register is $0x0000 upon hardware reset. imod?nterrupt mode. this bit determines if the 3 interrupt inputs are configured as ipl pins or irq pins for the mc68en302 and replace the mod bit functionality in the internal table 2-3. pin muxing operation mux bit bit = 0 pin function bit = 1 pin function pm0 amux brg1 pm1 ras0 brg2/sds2/pa7 pm2 ras1 brg3/pa12 pm3 cas0 pb0/ia ck7 pm4 cas1 pb1/ia ck6 pm5 dram_r w pb2/ia ck1 pm6 a0 t out1 /pb4 pm7 dreq /pa13 we l pm8 d a ck /pa14 weh pm9 oe done /pa15 1514131211109876543210 imod 0 0 0 mil iet7 iet6 iet1 00000000 mc68en302 module bus controller 2-4 mc68en302 reference manual motorola 302 gimr. for proper operation of the mc68en302, the mod bit must be zero in the internal 302 core. 0 = configures the pins as ipl2 -ipl0 . 1 = configures the pins as irq7 , irq6 , and irq1 . bits 14?2?eserved. should be written as zero. these bits are always read as zero. mil?odule interrupt level. this bit determines the interrupt level at which module bus controller interrupts are generated. because the interrupt level of the internal 302 core is set at 4, and this bit predetermines the module bus controller interrupt at either level 3 or 5, external interrupts should not be generated at level 4 or the level preset by mil. 0 = interrupts are generated at level 5 1 = interrupts are generated at level 3. iet7?nterrupt edge trigger level 7. this bit has no effect unless imod=1 and replaces the operation of the et7 bit in the global interrupt mode register (gimr) of the internal 302 core. the et7 bit in the gimr register must equal zero for correct interrupt operation 0 = an interrupt is made pending when irq7 is low. 1 = an interrupt is made pending when irq7 changes from a one to a zero (falling edge) of the mc68en302. iet6?nterrupt edge trigger level 6. this bit is has no affect unless imod is one. this bit replaces the functionality of the et6 bit in the global interrupt mode register (gimr) of the internal 302 core. the et6 bit in the gimr register must be set to zero. 0 = an interrupt is made pending when irq6 is low. 1 = an interrupt is made pending when irq6 changes from a one to a zero (falling edge). iet1?nterrupt edge trigger level 1. this bit is has no effect unless imod is one. this bit replaces the functionality of the et1 bit in the global interrupt mode register (gimr) of the internal 302 core. the et1 bit in the gimr register must be set to zero. 0 = an interrupt is made pending when irq1 is low. 1 = an interrupt is made pending when irq1 changes from a one to a zero (falling edge). bits 7??eserved. should be written as zero. these bits are always read as zero. 2.6 chip select extension registers (cser3?ser0) these registers provide additional functionality above the 68302 chip selects including 8-bit bus operation and parity generation and checking. before setting the fce, dt2?t0 or en8 bits, be sure that an external dtack is supported by programming the 302 dtack field in the corresponding or register to 111. these registers are initialized to 0x000c or 0x000d upon hard reset (refer to the en8 bit for more detail). if at reset , the 8-bit mode is selected through use of the parity1/busw pin, the dtack field in or0 of the 302 core is forced to 111. this results in the dt2?t0 field of cser0 controlling dtack. mc68en302 module bus controller motorola mc68en302 reference manual 2-5 during reset, cs1, cs2 and cs3 are disabled via the en bit in the br1, br2 and br3 registers. note that when in disable cpu mode, the cs0 function is replaced by iout2. bits 15??eserved. should be written to zero by the host processor. these bits are always read as zero. cspe?hip select parity enable. this bit enables parity checking and generation when the corresponding chip select is generated. unless the corresponding chip select is set to 8-bit operation, parity is generated and checked on both bytes. bits 6??eserved. should be written to zero by the host processor. this bit is always read as zero. fce?ast cycle enable. this bit enables fast mode operation. when using fast cycles, cs and as are not negated between 8 bits of a 16 bit transfer, allowing a 16-bit transfer to occur on an 8-bit bus in 5 clocks rather than 6. dt2?t0?tack. these bits are used to determine whether dtack is generated internally with a programmable number of wait states or externally by the peripheral. when done internally, the mc68en302 provides the option of allowing 16-bit accesses to take place in two-three clock external 8-bit accesses. the 68000 only sees a single six clock access internally during this mode of operation. this functionality is also referred to as ?inus one wait state option.?note that an 8-bit operand access requires a 4 clock bus cycle. table 2-4 shows how the bits are encoded. en8?nable 8-bit chip select. when set to a one, the 8-bit chip select operation is enabled. if the system is booted from an 8-bit memory, the system must drive the busw pin low during system reset which sets the en8 bit for all four cser registers. this assures that the device is able to access 8-bit memories as well as 16-bit memories. in 8-bit mode bits d15 d8 of the data bus are used. 1514131211109876543210 00000000 cspe 0 0 fce dt2 dt1 dt0 en8 table 2-4. dt bit encoding dt bit encoding wait states 000 -1 001 0 010 1 011 2 100 3 101 4 110 5 111 no dtack mc68en302 module bus controller 2-6 mc68en302 reference manual motorola 2.7 parity control and status register (pcsr) this register controls and gives the status of the parity checking portions of the parity circuitry. this register is set to 0x0000 upon hardware reset. pie?arity error interrupt enable. this bit determines if an interrupt is generated when a parity error is detected. 0 = no interrupt is generated. 1 = either a level 3 or level 5 interrupt is generated, depending upon the encoding of the mil bit in the ier register. opar?dd parity. this bit is used to determine if odd or even parity is used. 0 = parity is even. 1 = parity is odd. pec?arity error chip selects (pec3?ec0). these status bits indicate that there was a parity error in the corresponding chip select bank. if one of the three bits is set to one, a parity error is detected in the corresponding bank. if the pie bit is set, a level 5 (or 3) interrupt is driven to the processor as long as one of the pec3?ec0 bits are set. pec3?ec0 are sticky bits which are cleared when a one is written to them or upon hardware reset. writing a zero does not change the value of the pec bits. the paritye pin is asserted until the pec3?ec0 bits are all cleared. note if the parity pin enable bit (ppe in mbc csr) = 0 and parity is enabled with cspe in cser3?ser0, then a parity error will be reported on the associated pec bit. ped?arity error dram (ped1?ed0). these status bits indicate that there was a parity error in the corresponding dram bank. if one of the two bits is set to one, a parity error is detected in the corresponding bank. if the pie bit is set, a level 5 (or 3) interrupt is driven to the processor as long as one of the ped bits is set. ped are sticky bits which are cleared when a one is written to them or upon hardware reset. writing a zero does not change the value of the ped bits. writing a zero does not change the value of the ped bits. the paritye pin is asserted as long as a ped bit is set. note if the parity pin enable bit (ppe in mbc csr) = 0 and parity is enabled on the dram interface (pe1 and/or pe0 = 1 in dcr) then a parity error will be reported on ped1?ed0. piv?arity error interrupt vector (piv7?iv0). if the pie bit is set, a parity error generates a level 5 (or 3) interrupt. the piv bits determine what interrupt vector is returned in response to a level 5 (or 3) parity error interrupt. 1514131211109876543210 pie opar pec3 pec2 pec1 pec0 ped1 ped0 piv7 piv6 piv5 piv4 piv3 piv2 piv1 piv0 mc68en302 module bus controller motorola mc68en302 reference manual 2-7 2.8 bus interface the mbc is responsible for determining the source of the bus mastership (module bus, external 68k bus or internal 302 core) and for controlling the direction of the buses. the layer of buffering between the internal 302 and internal 68000 buses mimics the operation of the 68302 external bus, giving the module bus the appearance of an external master from the viewpoint of the internal 302 core. the mbc does not affect the operation of the bus outside the mc68en302 unless it arbitrates for that bus and is given bus mastership. the operation of the mbc as bus master is such that the bus external to the mc68en302 operates as if an existing 302 peripheral is bus master. this is accomplished by: providing i/o control at the pad which overrides the existing 68302 i/o control. intercepting the external arbitration signals and merging them with the mbc arbitration. 2.8.1 bus arbitration the mbc provides the circuitry which prioritizes the bus mastership requests in the following order (highest priority to lowest): external bus requests module bus requests (ethernet module) internal 302 core 2.9 dynamic bus sizing the mbc accommodates dynamic bus sizing by providing control to operate on the internal 68000 bus as a 16-bit device while simultaneously providing an 8-bit option externally. control is provided via the en8 bit in the cser3?ser0 registers and via the busw pin. the mbc routes data into the proper byte of the word d15?8, increments the address, and runs a second bus cycle. when reading and writing, the mbc will assure proper operation when performing even byte accesses, even word accesses, and odd byte accesses. figure 2-4 shows the read cases, and figure 2-5 shows the write cases. the even word access is the only case requiring two bus cycles. when an internal bus cycles is taking place, both as and the appropriate chip select will be in operation (except when fast cycles are used). the address is incremented only in the case of an even address access. because of this, the address increment only involves setting a0 to one. mc68en302 module bus controller 2-8 mc68en302 reference manual motorola figure 2-2. 8-bit external to 16-bit internal read note that an external access of 16-bits to an 8-bit port requires an external address increment as well as data muxing. it is generally recommended that external accesses using the 8-bit chip select extensions access only 8-bits at a time and access that data on the upper 8-bits of the bus. figure 2-3. 16-bit internal to 8-bit external write first bus cycle d15-8 latched external external terminated internally id15-8 id7-0 terminated internally external terminated internally second bus cycle increment address d15-8 id15-8 id7-0 d15-8 id15-8 id7-0 id15-8 id7-0 d15-8 even byte access even word access odd byte access even byte access even word access odd byte access first bus cycle d15-8 latched external external terminated internally id15-8 id7-0 terminated internally external terminated internally second bus cycle increment address d15-8 id15-8 id7-0 d15-8 id15-8 id7-0 id15-8 id7-0 d15-8 mc68en302 module bus controller motorola mc68en302 reference manual 2-9 2.9.1 bus cycle timing the 8-bit extension logic for dynamic sizing is programmable from -1 to 5 wait states, and allows the external logic to terminate the cycle. even word accesses are a special case which require specific control operations to allow the device to provide two external bus cycles. in some cases, the timing generated looks like two comparable 68000 cycles.there are two exceptions to this. first, the -1 wait state timing is a special case, since the 68000 bus is defined as a minimum 4 clock bus. the second exception is the fast cycle case. the -1 wait state case appears externally as two 16-bit 3 clock bus cycles. figure 2-4 shows the timing for the read case, while figure 2-5 shows the timing for writes. figure 2-4. word read with 3-clock 8-bit accesses figure 2-5. word write with 3-clock 8-bit accesses the fast cycle case differs from the normal cycle in that as and chip select do not negate between the first and second half of the 16-bit access, allowing the two bus cycles to be s2 s3 s4 s5 s0 s1 clock s0 s1 s2 s3 s4 s5 addr23-1 addr0 as /cs rw data uds /lds s2 s3 s4 s5 s0 s1 clock s0 s1 s2 s3 s4 s5 addr23-1 addr0 as /cs rw data uds /lds mc68en302 module bus controller 2-10 mc68en302 reference manual motorola reduced one extra clock. a0 is incremented one half clock earlier in this scheme to allow sufficient address access in the second portion of the bus cycle. figure 2-6 shows the fast cycle read case, while figure 2-7 shows the fast cycle write case. in order to use fast cycles with sram, the cs signal is high between cycles, accommodating a write to srams. figure 2-6. fast cycle word read with ? wait state figure 2-7. fast cycle word write with -1 wait state 2.9.2 bus error handling since the external bus may operate as an 8-bit bus, at the same time the internal bus operates as 16-bits, a bus error passed from the external bus to the internal bus does not specify which byte has been faulted. to assure that information is not lost, the bus error s2 s3 s4 s5 s0 s1 clock s0 s1 s2 s3 addr23-1 addr0 as /cs rw data uds /lds s2 s3 s4 s5 s0 s1 clock s0 s1 s2 s3 addr23-1 addr0 as rw data uds /lds cs mc68en302 module bus controller motorola mc68en302 reference manual 2-11 byte (bb) bit is provided in the mbc register. this bit reflects the state of a0 during the last bus error caused by an access to a byte peripheral. 2.9.3 retry handling in most cases, an mc68en302 retry is identical to 302 retry operation. if however, a retry occurs during the second bus cycle of a word access to an 8-bit port, the retry signal is passed to the initiating master. this causes both of the cycles to be retried, instead of just the second cycle. 2.10 parity logic the mc68en302 provides parity support to generate, check, and report parity and parity errors. 2.10.1 parity generation the mc68en302 provides the option of generating and checking parity for the 4 chip selects and the 2 dram banks. in the case of a write, parity is generated with one bit of parity per byte of data. the parity is output on the parity pins and delayed from other data by the propagation delay through the parity generator. 2.10.2 parity checking parity checking is performed on read accesses. if the 8-bit option of the chip select logic is used, parity is checked on only the upper 8-bits. in all other options, parity is checked on both bytes. 2.10.3 parity error reporting parity error reporting is accomplished via three mechanisms. parity error pin this pin is asserted when a parity error is detected. parity error detection does not occur with enough time to generate a bus error on the affected cycle. the parity error pin may be used with external circuitry to facilitate parity error handling. this pin is not negated until all the parity error register bits are cleared. parity error status bits there are 6 pcsr register bits dedicated to providing status on parity errors, corresponding to the 2 dram banks and the 4 chip selects. if a parity error is detected, the bit that corresponds to the module that generated the error is set. these bits are reset to zero and are cleared by writing a one. parity error interrupt the pie bit in the pcsr register is provided to allow the option of generating a level 5 (or 3) interrupt in the event that a parity error is generated. if this option is selected, the interrupt is driven after the error is detected until the parity error status bits are cleared. mc68en302 module bus controller 2-12 mc68en302 reference manual motorola 2.10.4 parity pin enable during hardware reset, the parity pin enable bit (ppe) in the mbc register (see 2.4 module bus control (mbctl)) is cleared, which results in the parity pins becoming inputs. each of the three pins is sampled for a different function, as shown in table 2-5. after exiting hardware reset, these pins are sampled to determine chip functions. pullup or pulldown resistors are required for presetting the desired state if the parity pins are to be later programmed as input/output pins. after hardware reset, the ppe bit can be set to enable the parity pins as outputs. the ppe bit should be set to enable parity even on reads. 2.11 interrupt support all module bus and module bus controller interrupts are at level 5 or at level 3 if mil is set (see 2.5 interrupt extension register (ier)). there are two sources of interrupts in the mbc: one is the ethernet controller; the second source is the parity error interrupt. the parity error interrupt is the higher priority of the two. if an interrupt acknowledge cycle is generated when both interrupts are asserted, the mbc responds to the parity error interrupt by driving its vector onto the internal 68000 bus. only after the parity error interrupt is cleared will the ethernet controller respond to an iack cycle. in order to accommodate an additional interrupt source within the mc68en302, an additional interrupt mode (imod) bit is provided in the mbc. this bit configures the interrupt pins as irq or ipl lines. this replaces the mod bit in the global interrupt mode register (gimr). this means that the existing mod bit in the global interrupt mode register (gimr) must always remain at zero. the imod bit in the ier register duplicates this function in the mbc. since the mbc generates a level 5 (or level 3) interrupt, and there is no way to resolve iack conflicts with the external circuitry, a level 5 (or level 3) interrupt should not be asserted externally. figure 2-8 summarizes the interrupt configuration and priorities. table 2-5. parity pin enable operation ppe = 0 pin function ppe = 1 pin function discpu parity0 busw parity1 threes paritye mc68en302 module bus controller motorola mc68en302 reference manual 2-13 figure 2-8. external and internal interrupt prioritization the mbc passes the interrupt vector (see 4.1.4 interrupt vector register (ivec)) from the module bus to the 68000 bus. 7 (highest) 6 4 3 2 000 001 irq7 irq6 ** * ** 101 * 5 1 (lowest) ** * 110 irq1 priority normal mode dedicated mode irq7 , irq6 , irq1 external external internal 302 external/mbc external mbc/external external interrupt level ipl2 ?pl0 source *priority level not available to an external device in this mode ** the level not selected by mil is available but not both level 3 and level 5. mc68en302 module bus controller 2-14 mc68en302 reference manual motorola motorola mc68en302 reference manual 3-1 section 3 mc68en302 dram control module 3.1 introduction the mc68en302, like its predecessor the mc68302, can be connected with dram-type memories easily. the difference in the mc68en302 lies in the dram control module (dcm), which was developed to provide seamless integration of the 68000 core with dram memories. the mc68en302 dram controller is able to support up to two 16-bit wide banks and an address range from 128kbytes to 8mbytes. selection between the two banks occurs externally through the mc68en302 ras1 ?as0 signals, and byte selection occurs via the cas1 ?as0 signals. the user is able to select cycle lengths ranging in duration from 4 to 7 clocks. the mc68en302 also provides programmable refresh rates which can range anywhere from 16 to 4096 system clocks, or be disabled altogether. 3.2 memory map table 3-1 shows the basic memory map of the dram control module registers. 3.3 dram configuration register (dcr) this register controls the specific operation of each bank of dram and is initialized to zero at hardware reset. bits 15?2?eserved. should be written to zero by the host processor. these bits are always read as zero. e1-e0?efresh enable bits. 0 = disable refresh operation in the corresponding dram bank 1 = enable refresh operation in the corresponding bank. table 3-1. dram controller registers address name mnemonic type fc moba + 010 dram configuration register dcr read/write s moba + 012 dram refresh register drfrsh read/write s moba + 014 dram bank 0 base address register dba0 read/write s moba + 016 dram bank 1 base address register dba1 read/write s 1514131211109876543210 0000e1e0pe1pe0p1p0w1w0wp1wp0 s/u1 s/u0 mc68en302 dram control module 3-2 mc68en302 reference manual motorola pe1-pe0?nable parity. 0 = parity is generated but not checked 1 = parity is generated on writes, and parity is checked on reads in the corresponding bank. if a parity error is detected the bus cycle is terminated with a bus error. note if the parity pin enable bit (ppe in mbc csr) = 0 and parity is enabled on the dram interface (pe1 and/or pe0 = 1 in dcr) then a parity error will be reported on ped1?ed0. p1-p0?as precharge bits. these bits control the minimum number of clocks the ras signal is precharged between bus cycles. table 3-3 shows the encoding for these bits. w1-w0?ait state bits. these bits control the number of wait states required for dram bank accesses. table 3-3 shows the wait state bit encodings. wp1-wp0?rite protect. this bit enables and disables write protection to a corresponding dram bank. 0 = the corresponding dram bank may be written. 1 = write access to the corresponding dram bank returns a bus error. s/u1-s/u0?upervisor/user. this bit determines whether the given dram bank decodes to supervisor space (fc = 6 & 5) or both supervisor and user (fc = 6 & 5 & 1 & 2) space. 0 = respond to supervisor accesses only 1 = respond to supervisor and user space. 3.4 dram refresh register (drfrsh) this register controls the operation of the refresh circuitry and is initialized to zero on hardware reset. table 3-2. precharge bit encodings p1 p0 precharge clocks 00 2 01 3 10 4 11 5 table 3-3. wait state bit encodings w1 w0 wait states 00 0 01 1 10 2 11 3 1514131211109876543210 00000000r7r6r5r4r3r2r1r0 mc68en302 dram control module motorola mc68en302 reference manual 3-3 bits 15??eserved. should be written to zero by the host processor. these bits are always read as zero. r7-r0?efresh count bits. the value stored in these bits is multiplied by 16 system clocks to determine the refresh period. the divide by 16 scheme provides sufficient range to address systems operating with standard dram at frequencies less than 2 mhz as well as systems utilizing low power dram running at frequencies greater than 25 mhz. all zeroes correspond to 4096 system clocks. 3.5 dram base address register (dba1-dba0) the base address registers for dram are two 16-bit registers which are initialized to zero at hardware reset. these registers hold both the base address of each bank and mask bits for determining which address bits initiate bus cycle accesses to the dram banks. a23-a17?ase address bits. the base address bits determine where the dram bank is located on 128 kbyte boundaries. these bits are compared with the corresponding addresses generated by the mc68en302 to determine if a given bus cycle accesses a particular dram bank. these bits are used in conjunction with the mask bits to determine the size and location of a given dram bank. bits 8??eserved. should be written to zero by the host processor. these bits are always read as zero. m22-17?ask bits. these bits are used in conjunction with the base address bits to determine the size and location of a given dram bank. 0 = the corresponding address bit is ignored. 1 = the address compare logic uses the corresponding address bit when determining if a bus cycle access occurs within the dram bank. v?alid bit. this bit is cleared to 0 at hardware reset. 0 = this dram bank is not valid 1 = data for the corresponding dram bank data is valid, and dram accesses are decoded by that bank? circuitry. 3.6 dram control module operation 3.6.1 reset operation refresh accesses continue if the ethernet module is reset and during the reset instruction (soft reset), but not during system (hardware) reset. 1514131211109876543210 a23 a22 a21 a20 a19 a18 a17 0 0 m22 m21 m20 m19 m18 m17 v mc68en302 dram control module 3-4 mc68en302 reference manual motorola 3.6.2 read and write cycle operation figure 3-1 shows two consecutive 4-clock accesses with a 2-clock precharge of ras . ras is negated one clock before cas to provide a longer precharge time between consecutive hits in a given bank. figure 3-1. consecutive four-clock accesses in some cases, a dram access is not possible in a 4-clock cycle. in still other cases, the precharge time of 2 clocks is not enough for the given dram. figure 3-2 shows two consecutive 5-clock accesses, with a 3-clock ras precharge. note that the dram signals are delayed in the second cycle with respect to the processor bus signals, allowing a longer ras precharge time. s2 s3 s4 s5 s6 s1 clock s0 s7 s0 s1 s2 s3 addr ras cas dramrw data/ as uds /lds s4 s5 s6 s7 amux s0 parity mc68en302 dram control module motorola mc68en302 reference manual 3-5 figure 3-2. five-clock accesses with three-clock precharge 3.7 refresh operation the mc68en302 supports cas before ras refresh but note that refresh operation is not synchronized to the bus activity. a special dramrw (read/write) pin is provided so that refresh may occur regardless of the state of the processor bus. only active bus cycles operating in the dram banks will prevent a refresh cycle. refresh occurs in both banks simultaneously. dram refresh is initiated during an idle state between bus cycles or during a bus cycle which does not access the dram. if refresh is required concurrent with a dram access, the mc68en302 will perform the access while holding off the refresh. after the mc68en302 initiates a refresh cycle, it must hold off dram accesses by inserting wait states until the ras precharge is complete following the refresh cycle. figure 3-3 shows a refresh cycle. in this case, there is a dram access waiting on the bus and the dram access must wait until after ras precharge. s2 s3 s4 w w s1 clock s0 s5 s6 s7 s0 s1 addr ras cas dramrw data/ as uds/lds s2 s3 s4 w w s5 s6 s7 ww amux parity mc68en302 dram control module 3-6 mc68en302 reference manual motorola figure 3-3. precharge with dram access active 3.8 dram controller i/o 3.8.1 control signal pins the en302 contains 8 dram specific signal pins: cas1 ?as0 , ras1 ?as0 , amux , and dramrw . 3.8.2 column address strobes (cas1 ?as0 ) these active low pins allow seamless interface to column address strobe (cas ) inputs on industry standard dram, providing cas for both bank 0 and bank 1 of the dram controller. two strobes support byte operations on the external 16-bit bus. cas0 corresponds to data pins d15-d8. cas1 corresponds to data pins d7?0. 3.8.3 row address strobes (ras1 ras0 ) these active low pins allow seamless interface to row address strobe (ras ) inputs on industry standard dram, providing ras for both bytes of a given dram bank. a particular bank corresponds to specific base address and control information programmed in the mc68en302 dram control registers (see 3.2 memory map for a description). ras0 corresponds to bank 0 and ras1 corresponds to bank 1. 3.8.4 dram read/write (dramrw ) this active low pin is asserted to signify that a dram write cycle is occurring. it is separate from the processor bus r/w so that precharge takes place without regard to the state of r/ w . s2 s3 s4 w w s1 clock s0 w addr ras cas dramrw as uds /lds s5 s6 s7 amux wwwwwww mc68en302 dram control module motorola mc68en302 reference manual 3-7 3.8.5 address mux (amux ) the amux pin is provided for implementing external address muxing circuitry so that external masters may access dram modules controlled by the mc68en302 dram controller. external address muxing must take place in this situation since an access to the mc68en302 as a slave always results in the addresses driven as an input, and does not output addresses to the dram module. another use for the amux pin would be implementations in which a linear dram space is required. 3.8.6 parity (parity1?arity0) these two pins are provided to support parity checking of dram. if enabled, parity is generated on writes and checked on reads. a parity error on a read generates a bus error. parity0 is used in connection with d15?8 and parity1 is used in connection with d7 d0. parity checking/generation is not supported for external bus masters. 3.8.7 muxing scheme to provide a simplified implementation of the address mux, a unique muxing scheme is provided. rather than providing programmability to change which addresses are muxed on a particular signal, a generic muxing scheme is provided so that one muxing scheme may be utilized by all supported dram bank sizes. table 3-3 shows the dram muxing scheme. the usage listed in the table is for typical operation. it is possible that some users may utilize the base address registers and the mask bits in a non-standard way. table 3-4. address muxing scheme processor address row address column address usage a9 9 1 used for all bank sizes a10 10 2 a11 11 3 a12 12 4 a13 13 5 a14 14 6 a15 15 7 a16 16 8 a18 18 17 used for 512k and up a20 20 19 used for 2m and up a22 22 21 used for 8m mc68en302 dram control module 3-8 mc68en302 reference manual motorola motorola mc68en302 reference manual 4-1 section 4 ethernet controller the mc68en302, like the mc68360 quicc, provides full duplex ethernet along with multiprotocol support on the scc channels. on the mc68en302, the ethernet controller is independent of the cpm and therefore the mc68en302 provides the ethernet channel in addition to the pre-existing 302 scc channels without sacrificing any scc pins. the ethernet controller consists of an 802.3/ethernet mac layer protocol machine with an internal cam, transmit and receive fifos, buffer descriptor memory and a dual channel dma controller. the buffer descriptor memory, cam and dma controller all interface to the module bus. a block diagram of the ethernet controller is shown in figure 4-1. features are: 802.3 ethernet compliant mac layer (1-10 mbps) with industry standard interface full-duplex operation 128 byte transmit and receive fifos collision retry does not generate extra bus bandwidth collision fragments automatically discarded 64 entry cam with optional hash mode buffer descriptor memory on-chip ethernet controller 4-2 mc68en302 reference manual motorola figure 4-1. ethernet controller block diagram 4.1 register description table 4-1 describes the ethernet controller memory map. table 4-1. ethernet controller memory map address name mnemonic type moba + 800 ethernet control register ecntrl read/write moba + 802 ethernet dma configuration register edma read/write moba + 804 maximum receive buffer length emrblr read/write moba + 806 interrupt vector register intr_vect read/write moba + 808 interrupt event intr_event read/write moba + 80a interrupt mask register intr_mask read/write moba + 80c ethernet configuration ecnfig read/write moba + 80e ethernet test register ether_test read/write moba + 810 address recognition control register ar_cntrl read/write moba + (812-9ff) reserved moba + a00 moba + bff cam entry table cet read/write moba + c00 moba + fff buffer descriptors table ebd read/write control status registers descriptor dual-port ram tx/rcv buffer descriptor control ethernet protocol machine receive fifo transmit fifo physical layer serial interface module bus address recognition dual-port ram transmit status system interface dma ethernet controller motorola mc68en302 reference manual 4-3 bits in the registers are r/w unless noted otherwise. unimplemented bits will return 0 on reads. if reserved memory locations are accessed, dtack is not returned. 4.1.1 ethernet control register (ecntrl) the ecntrl register controls mc68en302 ethernet controller operation. all implemented bits in this register are r/w. this register is $0000 following system reset. 15? reserved. should be written to zero by the host processor. these bits are always read as zero. gts?raceful transmit stop. 0 = no change in ethernet controller operation 1 = the ethernet controller will stop transmission after all frames that are currently being transmitted have completed. see gra in 4.1.5 interrupt event register (intr_event). ether_en?thernet enable. 0 = reception is immediately stopped and transmission ends following the appending of a bad crc to any frame currently being transmitted. buffer descriptor(s) corresponding to an aborted transmit frame are not updated following ether_en deassertion. in this situation, the dma, buffer descriptor and fifo control logic is reset along with the buffer descriptor and fifo pointers. 1 = the ethernet controller is enabled and reception and transmission of frames may occur. reset?thernet controller reset. 0 = a reset is performed locally within the ethernet controller. ether_en is cleared and all other ethernet controller registers take their reset values. during ethernet controller reset, the buffer descriptor table and the cam entry table can not be read or written. any transmission/reception currently in progress is abruptly aborted. 1 = the mc68en302 ethernet controller operates normally 4.1.2 ethernet dma configuration status register (edma) the edma register allows user control of the dma unit and may be written only when the ether_en bit in the ecntrl register is cleared. this register is cleared by a hardware reset. bderr 6??uffer descriptor error number. 15141312111098765432 1 0 0000000000000gts ether_en reset 15141312111098 7 6 5 43210 bderr<6:0> 0 bdsize<1:0> tsrly wmrk<1:0> blim<2:0> ethernet controller 4-4 mc68en302 reference manual motorola this read only field is the buffer descriptor number that was being accessed when a bus error occurred. see 4.1.5 interrupt event register (intr_event) for a description of the bus error handling. bit 8?eserved. should be written to zero by the host processor. this bit is always read as zero. bdsize1-0?uffer descriptor size. (r/w) 00 = 8 transmit buffer descriptors, 120 receive buffer descriptors 01 = 16 transmit buffer descriptors, 112 receive buffer descriptors 10 = 32 transmit buffer descriptors, 96 receive buffer descriptors 11 = 64 transmit buffer descriptors, 64 receive buffer descriptors bdsize controls the allocation of the44 128 on-chip buffer descriptors between the transmit and receive operations. typical implementations will set bdsize(1?) to 01 allowing 16 transmit buffer descriptors and 112 receive descriptors. tsrly?ransmit start early. (r/w) tsrly controls when the transmission of a frame will begin. typical applications will set tsrly to 0. 0 = frames do not begin transmitting until the transmit fifo has only wmrk bytes available (empty), where wmrk ranges from 96 to 120 bytes. 1 = the frame will begin transmitting after the wmrk number of bytes have been written to the transmit fifo where wmrk ranges from 8 to 32 bytes. this requires low bus latency to avoid transmit fifo underrun. wmrk1??ifo watermark. (r/w) 00 = 8 fifo bytes present or available 01 = 16 fifo bytes present or available 10 = 24 fifo bytes present or available 11 = 32 fifo bytes present or available the fifo watermark is used to control the start of a dma burst. in the receive direction, the dma state machine waits for either an end-of-frame (eof) or a wmrk number of bytes to be in the receive fifo prior to beginning a dma burst of data out of the mc68en302 to the host bus. in the transmit direction, the dma state machine waits for wmrk number of bytes tsrly wmrk<1:0> bytes in transmit fifo at start of transmission 0 00 120 001 112 0 10 104 011 96 100 8 101 16 110 24 111 32 ethernet controller motorola mc68en302 reference manual 4-5 of space to be available in the transmit fifo prior to beginning a dma burst into the mc68en302 transmit fifo. wmrk is typically set to 16. wmrk1?mrk0, when used in conjunction with blim2?lim0, allows the system designer to configure the mc68en302 device for expected bus latency. blim2?lim0?urst limit. (r/w) blim2?lim0 controls the maximum length of a dma burst in accesses from the bus interface unit. blim is typically set to 8 for 16 bit systems. 000 = 1 access 001 = 2 accesses 010 = 4 accesses 011 = 8 accesses 100 = 16 accesses 101 = 32 accesses 110 = 64 accesses 111 = unlimited 4.1.3 ethernet maximum receive buffer length (emrblr) the emrblr register determines the maximum size of all receive buffers. because the maximum frame is limited to 1518, only bits 10? are written by the user. the value written into the maximum receive buffer length register must account for the receive crc which is always written into the last receive buffer. to allow one maximum size frame per buffer, emrblr must be set to 0000010111101110 or larger. the emrblr must be evenly divisible by 2. to ensure this, bit 0 is forced low. only non-zero values are considered to be valid, therefore this register should be written after reset, but before ethernet operation is enabled. all implemented bits are r/w. this register is cleared upon a hardware reset. 5?1?eserved. should be written to zero by the host processor. these bits are always read as zero. mrbl?aximum receive buffer length. must be programmed to a non-zero value for operation. 0?eserved. must be written as zero by the host processor. this bit is always read as zero. 1514131211109876543210 00000 maximum receive buffer length 0 ethernet controller 4-6 mc68en302 reference manual motorola 4.1.4 interrupt vector register (ivec) the ivec register controls the interrupt vector generated by the ethernet controller during an interrupt acknowledge cycle. this register can only be written when the ether_en bit in the ecntrl register is cleared. this register is reset to $000f. 15??eserved. should be written to zero by the host processor. these bits are always read as zero. vg?ector granularity. 0 = the interrupt vector is not modified to reflect the cause of the interrupt. 1 = the interrupt vector is modified to indicate the cause of the interrupt, replacing the lower two bits of the interrupt vector according to the following table: if multiple interrupt sources are present simultaneously and vg = 1, the inv bits will be set based on the following priority (highest ot lowest); 1. time critical interrupt. 2. receive interrupt 3. transmit interrupt 4. non-time critical interrupt. for example, if both rxb and tfint interrupts are asserted, inv1?nv0 will equal 00. interrupt vector1? represent the values of the two lower bits placed on the data bus during an interrupt acknowledge cycle. vg is cleared by reset. inv7??nterrupt vector. inv is the eight bit vector that the ethernet controller places on the low byte of the data bus during an interrupt acknowledge cycle. 4.1.5 interrupt event register (intr_event) when an event occurs that sets a bit in the interrupt event register, and the corresponding bit in the interrupt mask register (intr_mask) is set, an interrupt will be generated. to clear 1514131211109876543210 00000000 inv<7:0> interrupt vector 1? cause examples 00 receive interrupt rfint, rxb 01 transmit interrupt tfint, txb 10 non-time critical interrupt hberr, babr, babt, gra, bod, eberr 11 time critical interrupt bsy ethernet controller motorola mc68en302 reference manual 4-7 a bit in intr_event, a one must be written to that bit position. writing a zero will not change the value of the bit. this register is cleared upon a hardware reset. 15?1?eserved. should be written to zero by the host processor. hberr?eartbeat error. when hbc is set, a heartbeat was not detected within the heartbeat window following a transmission. babr?abbling receiver error. indicates a frame longer than 1520 bytes was received. according to 802.3, frames should not exceed 1518 bytes but two bytes of slop is allowed. receive frames exceeding 1520 bytes in length are truncated to prevent receive buffer overflow. babt?abbling transmitter error. the transmitted frame length has exceeded 1520 bytes. this condition is usually caused by a frame that is too long being placed into the transmit data buffer(s). gra?raceful stop complete. a graceful stop, initiated by the setting of gts, is now complete. once the frame that was in progress when gts was set has transmitted, this bit is set. if the start of a second frame is in the fifo, gra will be set after the transmission of the second frame. gra is also set after eberr. bod?ackoff done. indicates that the backoff timer has expired. this interrupt is used only for production testing and should normally be ignored. (set boden = 0) eberr?thernet bus error occurred. indicates that a bus error occurred when the ethernet controller was bus master. the bderr bits in the edma register indicate which buffer descriptor was being used at the time of the bus error. once any frames currently in the transmit fifo have completed transmission and their status is written to the appropriate buffer descriptor, the gra bit is set. if no frames or only a partial frame is in the transmit fifo, the gra bit is set immediately causing the partial frame to become an underrun truncated with a bad crc. tfint?ransmit frame interrupt. indicates that a frame has been transmitted and that the last corresponding buffer descriptor has been updated. rfint?eceive frame interrupt. indicates that a frame has been received and that the last corresponding buffer descriptor has been updated. 1514131211109876543210 00000 hberr babr babt gra bod eberr tfint rfint bsy txb rxb ethernet controller 4-8 mc68en302 reference manual motorola bsy?usy interrupt. indicates that the start of a frame was detected but a receive buffer was not available in which to put the frame. if not corrected, this results in a fifo overflow, which is indicated by the ov bit in the receive buffer descriptor. txb?ransmit buffer interrupt. indicates that a transmit buffer descriptor with the i bit set in its status word has been updated. rxb?eceive buffer interrupt. indicates that a receive buffer descriptor with the i bit set in its status word has been updated. 4.1.6 interrupt mask register (intr_mask) the interrupt mask register provides control over which ethernet controller events generate an actual interrupt. the interrupt mask register is cleared on a hardware reset. 15?1?eserved. must be written to zero by the host processor. hbeen?eartbeat error interrupt enable. enable interrupts when hberr is set bren?abbling receiver interrupt enable. enable interrupts when babr is set bten?abbling transmitter interrupt enable. enable interrupts when babt is set. graen?raceful stop interrupt enable. enable interrupts when gra is set boden?ackoff done enable. enable interrupts when bod is set. this bit should always be cleared. eberren?thernet controller bus error enable. enable interrupts when eberr is set. tfien?ransmit frame interrupt enable. enable interrupts when tfint is set. rfien?eceive frame interrupt enable. enable interrupts when rfint is set. 15141312111098 7 6 5 43210 00000 hbeen bren bten graen boden eberren tfien rfien bsyen tbien rbien ethernet controller motorola mc68en302 reference manual 4-9 bsyen?usy interrupt enable. enable interrupts when bsy is set. tbien?ransmit buffer interrupt enable. enable interrupts when tbint is set. rbien?eceive buffer interrupt enable. enable interrupts when rbint is set. 4.1.7 ethernet configuration (ecnfig) the ethernet configuration register provides protocol configuration information to the ethernet controller and can be written only when the ether_en bit in the ecntrl register is clear. this register is cleared on a hardware reset. 15??eserved. should be written to zero by the host processor. these bits are always read as zero. rdt?eceive disable on transmit 0 = receive path operates independently of transmit. 1 = disable reception of frames while transmitting. the purpose of this bit is to block reception of frames while this node is transmitting. if fden = 1, this bit must be 0. if fden = 0, this bit should be 1, except when: 1. loop = 1 to select internal feedback. 2. an external loopback is being performed. 3. this node wants to receive its own transmit frames for monitoring purposes. hbc?eartbeat control. 0 = the heartbeat check is not performed. following end of transmission, the hb bit in the txbd will be cleared. 1 = the heartbeat check is performed. following end of transmission, if clsn is not asserted during the heartbeat window, the hb bit in the txbd will be set. fden?ull duplex enable. 0 = carrier sense and collision inputs are active, deference and collision handling is according to ieee 802.3 1 = frames are transmitted independent of carrier sense and collision inputs. 151413121110987654 3 210 000000000000rdthbc fden loop ethernet controller 4-10 mc68en302 reference manual motorola loop?oopback. 0 = no loopback operation is performed 1 = transmitted frames are looped back internal to the device and tena remains inactive (low). 4.1.8 ethernet test (ether_test) the ethernet test register controls various manufacturing test modes. test modes may be useful to some users, but in general it is not suggested that the user set these modes in normal operation. this register can only be written when the ether_en bit in the ecntrl register is cleared and it is cleared on a reset. 15??eserved. must be written to zero by the host processor. these bits are always read as zero. rngt?andom number generator test. this bit allows testing of the random number generation logic used in the transmit backoff process. to run the random number generator test, write $0080 to this register and then poll repeatedly. this bit will be changed by hardware from 1 to 0 within 15 m sec if the random number generator is operating properly. tbo?est backoff. 0 = normal operation of the random number generator logic. 1 = the random number generated by the transmit backoff logic is all ones. trnd?ransmit random number control. 0 = an internal oscillator clocks the random number generator (normal mode). 1 = the transmit clock is used to generate the ethernet random number. slot?lot time length. specifies the number of bytes in a slot time used in backoff determination. 0 = the number of bytes in a slot time is 64. 1 = the number of bytes in a slot time is 2. coll?orce collision. coll allows the collision logic to be tested. the device must be in the internal loopback mode for coll to be valid. 0 = no collision is forced. 1 = a collision is forced during the subsequent transmission attempt. this results in 16 total transmission attempts with a retry error reported in the transmit descriptor. 1514131211109876543210 00000000 rngt tbo trnd slot coll drty rws tws ethernet controller motorola mc68en302 reference manual 4-11 drty?isable retry. 0 = the mc68en302 performs retry error reporting normally. 1 = the mc68en302 does not perform any retries of a frame before reporting a retry error in the transmit descriptor for the frame. rws?eceive watchdog timer short. 0 = the receive watchdog timer operates normally 1= the receive watchdog timer is short cycled for test purpose causing the receive watchdog timer to expire, and a babr interrupt to be generated if more than 100 bytes in a frame are received. tws?ransmit watchdog timer short. 0 = the transmit watchdog timer operates normally. 1 = the transmit watchdog timer is short cycled for test purposes causing the transmit watchdog timer to expire and a babt interrupt to be generated if more than 100 bytes in a frame are transmitted. 4.1.9 ar control register (ar_cntrl) the ar control register controls ar memory operation and can be written only when the ether_en bit in the control register is clear. bits in this register are not changed if the ether_en bit in the control register is set. this register is set to the value $0000 on a reset. hash_en?ash mode enable. 0 = perfect-entry match mode is selected for all entries 1= hash mode is enabled instead of perfect matches on entries 62 and 63. index_en?ndex enable. 0 = the receive buffer data pointer is unmodified 1= pass either line number or hash index into the upper byte of the receive buffer descriptor? data pointer. mult1?ult0?ulticast and broadcast reception control. mult controls whether multicast frames are received. broadcast is the special multicast address of all ones. 15 14 1312 11 109876543210 hash_en index_en mult1?ult0 pa_rej prom 0000000000 mult1?ult0] accept multicast? accept broadcast? 00 if match in tables yes 01 if match in tables no 10 yes, all yes 11 no, none no ethernet controller 4-12 mc68en302 reference manual motorola pa_rej?hysical address reject. 0 = frames with physical addresses are accepted if there is a table match, either perfect or hash. 1 = frames with physical addresses are accepted if there is no perfect match. if a physical address has a hash match but not a perfect match, the frame will be accepted. this bit has no effect on frames with a multicast address. prom?romiscuous mode. 0 = frames are accepted only if they meet the hashing, perfect address match, or mult1?ult0 criteria 1 = all frames are accepted regardless of address matching or settings of mult1 mult0. 9??eserved. should be written as zero by the host processor. these bits are always read as zero. 4.2 ethernet buffer descriptors the data for the ethernet frames must reside in memory external to the mc68en302 device and is placed in one or more buffers. buffer descriptors contain pointers to each buffer and contain the current state of the buffer. the bds are located inside the mc68en302 in the dual port buffer descriptor ram so that the load on the processor bus is minimized. software ?roduces?buffers by allocating/initializing memory and initializing buffer descriptors in the bdram. setting the most significant bit (r for transmit and e for receive) in the most significant word of the buffer descriptor initializes the buffer. mc68en302 dma hardware constantly polls the bds and processes the buffers after they have been initialized. processing in the case of transmit indicates that the data in the buffers has been read into the mc68en302 and transmitted out the ethernet interface. processing in the case of receive indicates that data received from the ethernet interface has been placed into data buffers pointed to by the receive buffer descriptors. once dma is complete and the buffer descriptor status bits have been written, the most signficant bit of the buffer descriptor is cleared indicating that the buffer has been processed. software may either poll the bds or may rely on the buffer/frame interrupts to detect when the buffers have been consumed. the ether_en signal operates as a reset to the bd/dma logic. when ether_en is deasserted, the bd pointers are reset to point to the starting transmit and receive bds. the buffer descriptors are not initialized by hardware during reset. for proper operation, before setting the ether_en bit, initialize at least one transmit and receive buffer descriptor by setting the most significant word of the descriptor to $0000 (this does not result in any transmit or receive operation, but is considered to be initialization). because the dma polls buffer descriptor memory to determine if the r/e bits in the next available bd are set whenever ether_en=1, initializing ??buffers, requires software to initialize n+1 buffer descriptors, setting the most significant bit of the (n+1) th descriptor to 0. ethernet controller motorola mc68en302 reference manual 4-13 the bdsize field in the edma register allows the user to define up to sixty-four buffers for the transmit channel and up to one hundred twenty buffers for the receive channel. the total number of combined transmit and receive buffers is one-hundred-twenty-eight. each bd table, transmit and receive, forms a circular queue with separate transmit buffer descriptor and receive buffer descriptor pointers maintained in the hardware. the length of the circular queues may also be controlled by using the w (wrap) bit in the buffer descriptors. if the transmit fifo empties of data before the end of the frame, an underrun occurs and a bad crc is appended to the partially transmitted data. in addition, the un bit is set in the last bd of the affected frame. transmit underrun may occur if the ethernet controller can not access the 68000 bus or if the next bd in the frame is not available. during the receive process, if data from a frame is available but no bd is available, the bsy interrupt is generated, warning the user that data will soon be lost if a bd does not become available. if the receive fifo overruns because there is no available bd or the ethernet controller can not access the 68000 bus, then the last bd for the receive frame will have the ov bit set. 4.2.1 ethernet receive buffer descriptor (rx bd) the user initializes the e, w, i, and (optionally) ro bits in the first word and the pointer in 3rd and 4th words of the receive buffer descriptor. the ethernet controller writes the following status bits: first word: e, l, f, m, lg, no, sh, cr, ov and cl bits. the m, lg, no, sh, cr, ov and cl bits in the first word of the buffer descriptor are only modified by the ethernet controller when the l bit is set second word: the buffer length third word: the reason and arindex fields if the index_en bit in the ar_cntrl register is set. figure 4-2. ethernet receive buffer descriptor (rx bd) the first word of the receive buffer descriptor contains status and control information concerning buffer descriptor handling and data flow. these status and control bits are described in the following paragraphs. offset + 0 offset + 2 offset + 4 offset + 6 rx data buffer pointer - a15?0 data length cl ov cr sh no lg - - m - f l i w ro e 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 arindex reason a23?16 ethernet controller 4-14 mc68en302 reference manual motorola e?mpty, written by ethernet controller (=0) and user (=1). 0 = the data buffer associated with this bd has been filled with received data. a receive buffer descriptor also has the e bit set to 0 when data reception has been aborted due to an error condition. when e is set to 0, the status, length, reason and ar index fields are updated according to the event that just occured during reception. 1 = the data buffer associated with this bd is empty, or reception is currently in progress. ro?eceive buffer software ownership, written by user. this bit is provided as a software ownership bit, if needed. hardware does not alter the value of this bit. w?rap (final bd in table), written by user. 0 = this is not the last buffer descriptor in the rx bd table. 1 = this is the last buffer descriptor in the rx bd table. after this buffer has been used, the ethernet controller receives incoming data into the first bd in the table, allowing the user to use fewer buffer descriptors than the number programmed by bdsize. i?nterrupt, written by user. 0 = no interrupt is generated after this buffer has been filled. 1 = the rbint bit in the interrupt event register is set when this buffer has been completely filled by the ethernet controller, indicating that the internal 68000 core is free to process the buffer. l?ast in frame, written by ethernet controller. 0 = the buffer is not the last in a frame. 1 = the buffer is the last in a frame. f?irst in frame, written by ethernet controller. 0 = the buffer is not the first in a frame. 1 = the buffer is the first in a frame. m?iss, written by ethernet controller. this bit is set by the ethernet controller when the incoming frame is not matched by the internal address recognition but is accepted because the ethernet controller is operating in promiscuous mode (prom=1). the user can monitor the m-bit to quickly determine whether the incoming frame was destined to this station. this bit is valid only if the l-bit is set. the m-bit is valid even if index_en is not set. 0 = an address match in the cam or hash algorithm caused frame reception. 1 = no address match occured on the received frame - promiscuous mode operation caused frame reception. ethernet controller motorola mc68en302 reference manual 4-15 lg?x frame length violation, written by ethernet controller. a frame length greater than 1520 (maximum allowed receive frame length) was recognized. in this situation, note that only the first 1520 bytes are written to the data buffer. this bit is valid only if the l-bit is set. this frame should be discarded. no?x nonoctet aligned frame, written by ethernet controller. the received frame contained a number of bits which is not a multiple of 8, and the crc check that occurred at the preceding byte boundary generated an error. this bit is valid only if the l-bit is set. if this bit is set, the cr bit will not be set. this frame should be discarded. sh?hort frame, written by ethernet controller. the mc68en302 does not support sh and this bit is always cleared. this bit indicates that a frame length less than the minimum defined for this channel was recognized. this frame should be discarded. cr?x crc error, written by ethernet controller. this frame contains a crc error and is an integral number of octets in length. this bit is valid only if the l-bit is set. this frame should be discarded. ov?verrun, written by ethernet controller. a receive fifo overrun occurred during frame reception. during a fifo overflow, the status bits also in this word (m, lg, no, sh, cr, and cl) lose their normal meaning and are zero. this bit is valid only if the l-bit is set. this frame should be discarded. cl?ollision, written by ethernet controller. a collision occurred during frame reception and the frame was closed. this bit is set only if a late collision occurred. this bit is valid only if the l-bit is set. this frame should be discarded. data length, written by ethernet controller. data length indicates the number of octets written by the ethernet controller into this bd? data buffer. it is written by the ethernet controller upon the close of this bd. reason and arindex, written by ethernet controller. if index_en=1 in the ar_cntrl register, then the reason and arindex fields replace the most significant byte of the rx buffer pointer. the reason and arindex are available on all buffer descriptors for a frame when index_en is set, independent of the condition of the l and f bits. when index_en = 0 the reason and arindex fields are not modified by hardware. rx buffer pointer, written by user. the receive buffer pointer always points to the first location of the associated data buffer and must be a multiple of 2. the data buffer must reside in memory external to the ethernet controller. when index_en=1, the most significant byte of the receive buffer pointer is replaced by a reason and index field. when index_en=0, the receive buffer pointer is not modified. see 4.6.1 buffer descriptor modification for more details. ethernet controller 4-16 mc68en302 reference manual motorola 4.2.2 ethernet transmit buffer descriptor transmit data is presented to the ethernet controller through buffers referenced by transmit buffer descriptors. the ethernet controller confirms transmission operation through the r bit, and indicates error conditions through the other status bits in the most signficant word of the bd. the host software must initialize the r, w, i, l, tc, and (optionally) to bits in the first word, the length in the second word, and the buffer pointer in the third and fourth words. . figure 4-3. ethernet transmit buffer descriptor (tx bd) the tx bd fields are detailed below. the unused bits (15-8) in offset + 4 are not used by the hardware. these unused bits are r/w by software and are ignored by hardware. r?eady, written by ethernet controller and user. 0 = the data buffer associated with this bd is not ready for transmission, leaving the software free to manipulate this bd or its associated data buffer. the ethernet controller clears this bit after the buffer has been transmitted or after an error condition is encountered. 1 = the data buffer, which has been prepared for transmission by the user, has not been transmitted or is currently being transmitted. no fields of this bd may be written after this bit is set. to?ransmit buffer software ownership, written by user. this bit is provided as a software ownership bit, if needed. hardware does not alter the value of this bit. l?last (last bd for this frame) 0 = this is not the last bd for this frame and the ethernet controller sets r= 0 when the buffer has been dma? into the mc68en302. status bits are not modified. 1 = the ethernet controller sets r = 0 and modifies the def, hb, lc, rl, rc, un and csl status bits once the buffer has been dma? into the mc68en302 and frame transmission has completed offset + 0 offset + 2 offset + 4 offset + 6 tx data buffer pointer - a15?0 data length csl un rl lc tc l i w to r hb def 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rc a23?16 unused ethernet controller motorola mc68en302 reference manual 4-17 w?rap (final bd in table), written by user. 0 = this is not the last buffer descriptor in the tx bd table. 1 = this is the last buffer descriptor in the tx bd table. after this buffer has been used, the ethernet controller transmits data from the first bd in the table. the maximum number of tx bds in this table is programmable through the bdsize bits. i?nterrupt, written by user. 0 = no interrupt is generated after this buffer has been serviced. 1 = tbint is set in the ethernet event register after this buffer has been serviced. if enabled through the mask register, this bit can cause interrupts to the host. l?ast in frame, written by user. 0 = the buffer is not the last in the transmit frame. 1 = the buffer is the last in the transmit frame. tc?x crc, written by user (only valid if l = 1). 0 = end transmission immediately after the last data byte. 1 = transmit the crc sequence after the last data byte. def?efer indication, written by ethernet controller (only valid if l = 1). the ethernet controller had to defer while attempting frame transmission. def is not set if a collision occurs during transmission. hb?eartbeat error, written by ethernet controller (only valid if l = 1). the collision input was not asserted within the heartbeat window after transmit completion. hb may be set only if hbc is not set in the ecnfig register. lc?ate collision, written by ethernet controller (only valid if l = 1). a collision has occurred after 56 data bytes have been transmitted. the ethernet controller terminates the transmission. rl?etransmission limit, written by ethernet controller (only valid if l = 1). the transmitter has failed (retry limit + 1) attempts to successfully transmit a message due to repeated collisions on the medium. rc?etry count, written by ethernet controller (only valid if l = 1). these four bits indicate the number of retries required before this frame was successfully transmitted. if rc = 0, then the frame was transmitted correctly the first time. if rc = 15, then the frame was transmitted successfully while the retry count was at its maximum value. if rl is set, then rc has no meaning. un?nderrun, written by ethernet controller (only valid if l = 1). a transmit fifo underrun occurred while transmitting one or more of the the data buffers associated with this frame. when fifo underrun occurs, frame transmission halts once an incorrect crc is appended. the remaining buffer(s) associated with this frame are dma? and dumped by the transmit logic. ethernet controller 4-18 mc68en302 reference manual motorola csl?arrier sense lost, written by ethernet controller (only valid if l = 1). carrier sense dropped out or was never asserted during a collision free frame transmission. data length, written by user. data length is the number of octets the ethernet controller should transmit from this bd? data buffer. it is never modified by the ethernet controller. the value of this field must be greater than zero. tx buffer pointer, written by user. the transmit buffer pointer containing the address of the associated data buffer, may be even or odd. the buffer must reside in memory external to the mc68en302. this value is never modified by the ethernet controller. 4.3 dma and buffer descriptor logic the dma and buffer descriptor modules transfer data between external memory and the tx/ rx fifos. 4.3.1 buffer descriptor logic buffer descriptors are stored in the on-chip dual-port ram. the ram is sufficient to store 128 buffer descriptors of 4 sixteen-bit-words. the features of the bd circuitry are as follows: flexible buffer descriptor allocation between transmit and receive; multiple buffers per frame transmit buffers may start on any byte boundary, receive buffers must start on even byte boundaries. maximum receive buffer size is user controllable; the buffer descriptor space is divided between transmit and receive in various configurations depending on the value of bdsize in the edma register. table 4-2 shows the starting and ending addresses (offset from moba) in the bd ram for the four options. the maximum receive buffer length field (mrbl) in the emrblr register determines the default length of all receive buffers besides the last buffer of a frame (the last buffer is usually shorter in length than the preceding buffers). on the transmit side, the mc68en302 may have up to two separate frames with open buffers at a specific point in time. while the first frame completes the transmit process, dma table 4-2. bd ram address ranges bdsize transmit buffer descriptor range receive buffer descriptor range number of transmit buffers number of receive buffers $00 $c00 - $c3f $c40 - $fff 8 120 $01 $c00 - $c7f $c80 - $fff 16 112 $10 $c00 - $cff $d00 - $fff 32 96 $11 $c00 - $dff $e00 - $fff 64 64 ethernet controller motorola mc68en302 reference manual 4-19 operaton begins for the second frame as the frame status of the first frame is determined. frame status is not available until after the 4 microsecond heartbeat window at the end of transmission. when ether_en changes from 0 to 1, the transmit process starts at buffer descriptor+ $c00 and the receiver begins processing bds at offset $ c40, $ c80, $ d00, or $ e00 depending on bdsize. when gts (graceful transmit stop) is set, the transmitter halts once any unfinished transmit frames have completed transmission and the buffer descriptors have been updated. the transmitter then generates a gra interrupt. when gts is cleared (0), the transmitter begins transmission with the next frame in the transmit queue. 4.3.2 dma logic the dma block transfers data between the fifos and the data buffers that buffer descriptors point to. the dma block must arbitrate for access to the module bus. once the module bus controller has received a grant for the 68000 bus, a module bus grant is passed to the dma controller. the dma controller alternates between transmit and receive dma, passing over either one if there is no outstanding data. if there is receive data but no available buffer to place the data in, a bsy (busy) interrupt is generated. once a data flow direction is chosen between transmit and receive, the dma machine continues to read a word or byte until it releases the bus and returns to the idle state. the dma machine will release the bus on any of the following conditions: the burst limit counter is reached. an end of frame (eof) has been reached. the receive fifo has been emptied. the transmit fifo has been filled. at the end of a buffer. at the beginning or end of a buffer, a byte access occurs if necessary. once the dma machine releases bus mastership, if additional data must be moved, the dma machine generates another bus request. 4.4 transmit and receive fifos the ethernet controller contains separate 128-byte transmit and receive fifos organized as 64 locations x 18 bits each with 16 bits for data and 2 for tag information. each fifo has independent control logic allowing full duplex operation. 4.4.1 transmit fifo the transmit fifo control logic provides flow control information to the transmit buffer descriptor logic. the timing for new transmit dmas depends upon the wmrk and tsrly bits in the edma register as well as the number of locations currently available in the fifo. ethernet controller 4-20 mc68en302 reference manual motorola the transmit fifo control logic provides a signal indicating data is available to the ethernet transmit protocol machine. if underflow occurs, the ethernet transmit protocol machine will handle aborting the frame (append a bad crc) and flushing the remainder of the frame from the fifo. if a collision occurs within the slot time in a transmit frame, the fifo supports retry by maintaining a separate start of frame pointer (read lag pointer). new data is never written on top of start of frame data until the slot time has passed. two control signals pass between the ethernet transmit logic and the transmit fifo to indicate when the slot time (collision window) has been passed (transmit accept) or when a collision retry must take place (transmit retry). 4.4.2 receive fifo the receive fifo control logic provides ?ata available?and ?eceive fifo empty?flow control signals to the receive dma controller. the ?ata available?signal is asserted as a function of the number of bytes available in the fifo and the wmrk bits from the edma register. if overflow occurs, the status word will have the ou bit set which will be written into the receive bd. the frame should be discarded by software. data is written into the receive fifo by the ethernet receive logic in the case of status information, and by the address recognition logic if the reason and arindex fields are enabled. the receive fifo control logic maintains a ?tart of frame?pointer that allows purging collision fragments from the fifo so that they need not be dma?. this purging of fragments (runt frames less than 64 bytes long) is automatic and cannot be disabled. 4.5 ethernet protocol logic this block implements the mac (media access control) sublayer of the ieee 802.3 standard, supporting operation up to 10 mbps compliant with both ethernet and 802.3 standards. this logic is subdivided into transmit, receive and loopback/serial interface sections. 4.5.1 ethernet transmit the ethernet transmiter block performs the following functions: parallel to serial conversion of data encapsulation of transmit frames generation of preamble (pa) and start of frame delimiter (sfd) transmits serial data from the transmit fifo interface pads short frames (with 0?) appends crc, if required appends bad crc if required appends jam pattern (all 1?) transmit protocol ethernet controller motorola mc68en302 reference manual 4-21 guarantees minimum inter-frame gap (ifg) of 9.6 m sec between carriersense deasserted and next frame transmitted. provides 8 byte pa + sfd appends 32 bit jam sequence (all 1?) and start backoff timer upon collision appends 32 bit crc (if tc = 1) or bad crc if aborting frame defers to carriersense for 6 m sec, then ignores carriersense for 3.6 m sec during interframegap collision retry occurs under the 802.3 truncated binary exponential backoff algorithm detects a babbling transmission and generates babt interrupt aborts frame transmission if transmit fifo underflow, ether_en deassertion during frame transmission, collision retry limit exceeded, late collision or collision and drty = 1 provides transmit frame status generates the def, hb, lc, rl, rc, un and csl status fields written into the end of frame transmit buffer descriptor which provide status on the transmission of the frame. the definition of these fields is based on the layer management section of the 802.3 standard. these fields are valid after the heartbeat window following the successful transmission of a frame or if the collision retry limit (16 attempts) is exceeded. a ?mitstatusready?signal is asserted to the transmit buffer descriptor control logic when this status is available all logic in the ethernet transmit block runs synchronously with the ethernet tclk provided by an external ethernet physical layer component(s). note deasserting ether_en during frame transmission is not recommended as ether_en is used as a reset signal in the ethernet controller logic. the recommended procedure is to assert the gts bit to gracefully halt transmission. once the gra interrupt is received indicating that transmission has completed, then deassert ether_en. 4.5.2 ethernet receive the receive block consists of the following submodules: serial to parallel conversion receive protocol control controls data path by stripping pa, sfd, and dribble bits detects runt frames, and signals reject to the receive fifo detects giant frames, generates the babr interrupt and discards the rest of frame provides count to determine frame length (in bytes) provides for interframe recovery if a minimum receive interframe gap of approximately 2.4 m sec is provided. ethernet controller 4-22 mc68en302 reference manual motorola receive frame status generates the m, lg, no, sh, cr, ov and cl status fields which are written into the end of frame receive buffer descriptor to provide status on the reception of the frame. the definition of these fields is based on the layer management section of the 802.3 standard. the serial interface consists of tclk, tena, tx, rclk, rena, rx and clsn. the polarity of the tena, tx, rena, rx and clsn signals is positive (1 or asserted = voh or vih). zero or more rclk cycles are required following the deassertion of rena at the end of a receive frame. logic in this module will detect end of receive frame condition and switch in tclk if necessary to complete flushing the frame through the receive data path and into the receive fifo. 4.5.3 ethernet loopback the transmit to receive loopback function is selected by the loop bit in the ecnfig register. while in the internal loopback mode, tena will not assert. any assertion of rena and clsn will be ignored. 4.6 ethernet ar (address recognition) the mc68en302 supports 64-entry internal address recognition with 48 bit address matching for receive address filtering. address recognition memory is written as a normal memory cycle. note that unused entries in the ar memory map do not return dtack if accessed. there are two modes for address recognition: perfect entries, and hash mode. the mode selected determines the way in which memory is partitioned. when perfect-entry mode is selected, the entire memory is devoted to storing addresses for 64 perfect matches. when hash mode is selected, 8 bytes are used to store a logical address filter, and 372 bytes are used to store addresses for 62 perfect matches. in hash mode, a logical address filter mask is used which requires the processor to perform final filtering. as the incoming data stream goes through the crc generator, once the 48th bit of the destination address has passed this circuitry, the six most significant bits of the crc are sampled. those 6 bits become an address which selects one of the 64 bits in the logical address filter mask. if the mask bit selected is a ?? the address matches and the packet is accepted. when programming the hash table, the task of mapping a destination address to one of 64 bit positions requires a computer program to generate the crc codes for the addresses desired. the 6 most significant bits of a given addresses?crc becomes the pointer into that addresses?hash table entry. for ethernet, the crc polynomial is crc32 or: x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1 there is no rule on what type of address can be used in which type of address matching mode. either physical or multicast addresses may be stored as either a perfect match or hash table entries. if an address matches both a perfect entry and a hash entry, the perfect entry takes precedence. ethernet controller motorola mc68en302 reference manual 4-23 broadcast and multicast frames may be either unconditionally accepted or unconditionally rejected. note that multicast frames may be conditionally accepted based on a matching table entry, either perfect or hash. refer to figure 4-4 and table 4-3 for broadcast and multicast frame address recognition. physical addresses are compared to perfect-match entries and either accepted or rejected. if no perfect match occurs, the addresses may then be accepted (but not rejected) on the basis of a hash match. refer to figure 4-4 and table 4-4 for physical address recognition. a physical address, but not a multicast address, may be rejected on the basis of a perfect match. a hash table match alone on a physical address is not sufficient to reject that frame. the address recognition memory is not initialized at reset; the user must initialize it before setting ether_en in ecntrl. perfect-match entries which are unused should be set to all 1? (broadcast address) which is a safe value since broadcast frame handling occurs independently of any table entries. unused hashmode entry bits must be set to 0. 4.6.1 buffer descriptor modification index values and reason fields may be passed into the upper byte of the receive buffer descriptor? data pointer by setting the index_en bit. this may help improve software efficiency. if index_en is cleared, the receive buffer descriptor data pointer is not modified by the mc68en302. if index_en is set, the index value and reason field will be written into all the bds of a frame. there are four reasons, not counting promiscuous mode, which cause a frame to be accepted: 1. the frame is a multicast or broadcast frame and the appropriate mult bits are set. 2. a perfect address match occurs. 3. a hash match occurs. 4. no perfect match occurs, the frame has a physical, not multicast address, and the pa_rej bit is set. ethernet controller 4-24 mc68en302 reference manual motorola table 4-3. unicast address processing control operation prom pa_rej ar result accept/rej miss ar reason index 0 0 perfect match a 0 10 line # hash match a 0 11 hash index no match r 0 1 perfect match r hash match a 0 11 hash index no match a 0 00 hash index 1 0 perfect match a 0 10 line # hash match a 0 11 hash index no match a 1 00 hash index 1 1 perfect match a 1 00 hash index hash match a 0 11 hash index no match a 0 00 hash index table 4-4. broadcast and multicast address processing control broadcast multicast prom mult1 mult0 accept/ reject miss ar reason index ar result accept/ reject miss ar reason index 0 00 a 0 01 0x3f perfect match a 0 10 line # hash match a 0 11 hash index no match r 0 01 r same as above entries 0 10 a 0 01 0x3f perfect match a 0 10 line # hash match a 0 11 hash index no match a 0 01 0x00 011 r r 1 00 a 0 01 0x3f perfect match a 0 10 hash match a 0 11 no match a 1 00 1 01 a 1 00 0x2f same as above entries 1 10 a 0 01 0x3f perfect match a 0 10 line # hash match a 0 11 hash index no match a 0 01 0x00 1 11 a 1 00 0x2f a 1 00 hash index ethernet controller motorola mc68en302 reference manual 4-25 figure 4-4. ethernet address recognition flowchart 4.6.2 writing addresses into tables the address recognition block is written/read just like a normal memory cycle (word or byte). unused locations do not return dtack if accessed. check address broadcast addr? yes mult[0] = 0? yes receive frame reason = 01 arindex = 111111 prom = 1? no no discard frame no perfect match? no yes receive frame reason = 11 arindex = hash yes no hash match? receive frame reason = 10 arindex = matching line number index multicast addr? no yes mult[10] = 10? yes receive frame reason = 01 arindex = 000000 pa_rejt = 1? yes no yes receive frame reason = 00 arindex = hash index no receive frame reason = 00 arindex = hash index set miss bit multicast addr & mult[10] = 11? no yes physical addr & pa_rejt = 1? yes no ethernet controller 4-26 mc68en302 reference manual motorola because each entry in the perfect-match table is 48 bits, but no more than 16 bits can be written at a time; byte 5(or the word consisting of bytes 4 and 5 of a perfect-match entry) must be written last. this prevents an address compare from occurring on partially-written entries. when the first byte (or word) of an entry is written, that entry is temporarily disabled until byte 5 (or a word consisting of bytes 4 and 5) is written. the address recognition memory map for perfect match mode is shown in figure 4-5. the least significant bit of byte 0 (bit 8 of word moba + $a00, +$a08,...) corresponds to the i/g address bit - this is the first bit received off the wire. the order of the bits received starts with byte 0-bit0 and continues through byte0-bit7. the next byte is received as byte1-bit0, byte1-bit1,...byte1-bit7 up through byte 5. figure 4-5. ar memory map - perfect match mode when hash_en is set, the last two entries in the table are used for the logical address filter mask bits. hash index 0 is located in the least significant bit of byte 7 in the hash table (moba + bfb). hash index 63 is bit 7 of byte 0 (moba + bf0) in the hash table. when writing logical address filter mask bits there is no restriction on the ordering of the writes. when hash_en is set, the memory map is changed as shown in figure 4-6. when hash_en is set, locations moba + bf4, + bf6 and moba + bfc, +bfe should not be read or written to (dtack will not be returned). moba +$ a00 moba + $a02 moba + $a04 moba + $a06 byte 5 byte0 unused unused first entry moba + $a08 moba + $a0a moba + $a0c moba + $a0e byte 5 byte 0 unused unused second entry moba + $bf8 moba + $bfa moba + $bfc moba + $bfe byte 5 byte 0 unused unused last entry byte 1 byte 2 byte 3 byte 4 ethernet controller 4-27 mc68en302 reference manual motorola figure 4-6. ar memory map - hash mode 4.6.3 reading addresses from tables the address recognition block is read as a normal memory cycle. there is no restriction on the order of bytes to be read. moba + $a00 moba + $a02 moba + $a04 moba + $a06 byte 5 byte 0 unused unused first entry moba + $bf0 moba + $bf2 moba +$ bf4 moba + $bf6 0 unused unused first four moba + $bf8 moba + $bfa moba + $bfc moba + $bfe unused unused unused unused unused unused bytes of hash last four bytes of hash 1 3 2 4 6 5 7 ethernet controller 4-28 mc68en302 reference manual motorola motorola mc68en302 reference manual 5-1 section 5 signal descriptions this section contains descriptions of the mc68en302 signals using the mc68302 as a reference. 5.1 pin/signal combinations the following table defines the mc68en302 signals and the pinouts of the 144 pin tqfp package. the pga package has several exclusive signals not included on the tqfp package. the signals exclusive to the pga package are iac, frz and two temperature sense pins which are internally connected to each other. table 5-1. mc68en302 144-tqfp pin/signal definition tqfp pin signal(s) type 1 tin2/pb5 bidir 2 a0/tout1 /pb4 bidir 3 vcc1 pwr 4 tin1/pb3 bidir 5 dramrw /pb2/iack1 bidir 6 cas1 /pb1/iack6 bidir 7 cas0 /pb0/iack7 bidir 8 gnd1 pwr 9 uds bidir 10 lds bidir 11 as bidir 12 rw bidir 13 gnd2 pwr 14 xtal out 15 extal in 16 vcc2 pwr 17 clko out 18 ipl0 /irq1 in 19 ipl1 /irq6 in 20 ipl 2/irq7 in 21 berr bidir 22 avec /iout0 bidir 23 reset bidir 24 halt bidir 25 br bidir 26 bgack bidir 27 bg bidir pga only tpad1 (temp_sense) 28 tms in signal descriptions 5-2 mc68en302 reference manual motorola 29 tck in 30 trst in 31 dtack bidir 32 gnd3 pwr 33 vcc3 pwr 34 rclk1/l1clk bidir 35 tclk1/l1sy0/sds1 bidir 36 txd1/l1txd out 37 rts1/l1rq/gcidcl out 38 rts3/sptxd out 39 cd3/spclk bidir 40 amux /brg1 out 41 gnd in 42 parity1/busw bidir 43 parity0/discpu bidir 44 vcc4 pwr pga only frz in 45 gnd4 pwr 46 paritye /threestate bidir 47 wel/dreq /pa13 bidir 48 weh/dack /pa14 bidir 49 oe /done/pa15 bidir 50 ras1 /brg3/pa12 bidir 51 ras0 /brg2/sds2/pa7 bidir 52 gnd5 pwr 53 tclk3/pa11 bidir 54 rclk3/pa10 bidir 55 txd3/pa9 bidir 56 rxd3/pa8 bidir 57 vcc5 pwr 58 cd2/pa6 bidir 59 rts2 /pa5 bidir 60 cts2 /pa4 bidir 61 gnd6 pwr 62 tclk2/pa3 bidir 63 rclk2/pa2 bidir 64 txd2/pa1 bidir 65 rxd2/pa0 bidir 66 rxd1/l1rxd in 67 cts1/l1gr in 68 cd1/l1sy1 in 69 cts3/sprxd in 70 rx bidir 71 rena bidir 72 tx out 73 vcc6 pwr 74 gnd7 pwr 75 clsn in 76 rclk in 77 tena out table 5-1. mc68en302 144-tqfp pin/signal definition signal descriptions motorola mc68en302 reference manual 5-3 78 tclk in 79 d0 bidir 80 d1 bidir 81 d2 bidir 82 d3 bidir 83 gnd8 pwr 84 d4 bidir 85 d5 bidir 86 d6 bidir 87 d7 bidir 88 vcc7 pwr 89 d8 bidir 90 d9 bidir 91 d10 bidir 92 d11 bidir 93 gnd9 pwr 94 d12 bidir 95 d13 bidir 96 d14 bidir 97 d15 bidir 98 gnd10 pwr 99 vcc8 pwr 100 a23 bidir 101 a22 bidir 102 a21 bidir 103 a20 bidir 104 gnd11 pwr 105 a19 bidir 106 a18 bidir 107 a17 bidir 108 a16 bidir 109 vcc9 pwr 110 a15 bidir 111 a14 bidir 112 a13 bidir 113 a12 bidir 114 gnd12 pwr 115 a11 bidir 116 a10 bidir 117 a9 bidir 118 a8 bidir 119 a7 bidir 120 a6 bidir 121 a5 bidir 122 a4 bidir 123 gnd13 pwr 124 a3 bidir 125 a2 bidir 126 a1 bidir 127 fc0 bidir table 5-1. mc68en302 144-tqfp pin/signal definition signal descriptions 5-4 mc68en302 reference manual motorola 5.2 mc68en302/mc68302 common signals the following pin/signal combinations are common between the mc68302 and mc68en302. any differences in functionality are noted. a23?1 d15?0 in 8-bit mode bit 15?it 8 is used on the mc68en302 rather than bit 7?it 0 on the mc68302. all 16 bits of the data bus are driven during an 8-bit write. r/w as uds a0 is not multiplexed with uds on the en302 lds dt ack a vec /iout0 ipl2 /irq7 ipl1 /irq6 ipl0 /irq1 fc2?c0 br bg bgack berr reset hal t tclk3 /pa11 128 vcc10 pwr 129 fc1 bidir 130 fc2 bidir 131 cs0 /iout2 out 132 cs1 out 133 gnd14 pwr 134 cs2 out 135 cs3 out pga only tpad2 (temp_sense) 136 tdo out 137 tdi in pga only iac out 138 pb11 bidir 139 pb10 bidir 140 pb9 bidir 141 pb8 bidir 142 wdog /pb7 bidir 143 gnd15 pwr 144 tout 2/pb6 bidir table 5-1. mc68en302 144-tqfp pin/signal definition signal descriptions motorola mc68en302 reference manual 5-5 rclk3 /pa10 txd3 /pa9 rxd3 /pa8 cd2 /pa6 r ts2 /pa5 cts2 /pa4 tclk2 /pa3 rclk2 /pa2 txd2 /pa1 pb11?b8 wdog /pb7 t out2 /pb6 tin2/pb5 tin1/pb3 rxd1/l1rxd txd1/l1txd rclk1/l1clk tclk1/l1sy0/sds1 cd1 /s1sy1 cts1 /l1gr r ts1 /l1rq/gcidcl cd3 /spclk cts3 /sprxd r ts3 /sptxd cs3?s1 cs0/iout2 clko xtal extal 5.3 mc68302 signals removed or redefined the following signals that are present on the mc68302 are not present on the mc68en302 or have been redefined in some way. rmc/iout1 iac bclr frz busw discpu 5.3.1 rmc/iout1 this mc68302 output is not available on the mc68en302. signal descriptions 5-6 mc68en302 reference manual motorola 5.3.2 iac this mc68302 output is not available on the mc68en302 in the 144-pin tqfp package. it is available in the pga package. 5.3.3 bclr this mc68302 signal is not available on the mc68en302. the additional en302 logic monitors the bclr signal from the 302 core, but does not drive it. 5.3.4 frz this mc68302 input is now pulled up internally and is not available on the mc68en302 in the 144 pin tqfp package. it is available in the pga package. 5.3.5 busw the busw signal (bus width) is a dedicated pin on the mc68302, but is muxed with parity1 on the mc68en302. this pin functions as busw only during system reset. if the busw signal is low during en302 reset, the en8 bits in the cser3?ser0 register are set. the busw signal is not passed to the 302 core on the mc68en302, since the 302 core of the mc68en302 always operates in 16-bit mode. in 8-bit mode, bits d15?8 of the data bus are used. this is in contrast with the mc68302, which uses bits d7?0 in 8-bit mode. 5.3.6 discpu the discpu signal is a dedicated pin on the mc68302 but is muxed with parity0 on the mc68en302. this pin is discpu only during system reset. 5.4 mc68en302 new signals muxed with existing mc68302 signals several pins on the mc68en302 have enhanced mc68302 functionality. the additional signal capability is controlled by the pm9?m0 field in the mbctrl (module bus control) register. table 5-2. pin muxing control pm[i] mc68en302 pm[i]=0 mc68en302 pm[i]=1 mc68302 0 amux brg1 brg1 1 ras0 brg2/sds2/pa7 brg2/sds2/pa7 2 ras1 brg3/pa12 brg3/pa12 3 cas0 pb0/iack7 pb0/iack7 4 cas 1 pb1/iack6 pb1/iack6 5 dramrw pb2/iack1 pb2/iack1 6 a0 tout1/pb4 tout1 /pb4 7 dreq /pa13 wel dreq /pa13 8 dac k/pa14 weh dack /pa14 9oe done /pa15 done /pa15 signal descriptions motorola mc68en302 reference manual 5-7 5.4.1 amux - dram address mux the amux pin is an output only pin provided for implementing external address muxing circuitry when accessing dram. the user may require use of this signal if external masters are utilizing the en302 dram controller. when performing an access to the en302 as a slave, the address is driven as an input, preventing the en302 dram controller from driving the address bus. because of this, external muxing must take place. the amux pin is also useful in implementations where a linear dram space is required. the amux signal appears on the pin if the pm0 bit of the mbctrl = 0. if pm0 = 1 then the pin becomes brg1 instead. 5.4.2 ras0 - dram row address select, bit zero when the pm1 bit of the mbctrl = 0, this active low output signal is used to select one of two banks of dram as determined by the dram base address register 0 (dba0). if pm1 = 1 then the pin becomes brg2/sds2/pa7 and is bidirectional depending on the function chosen 5.4.3 ras1 - dram row address select bit 1 when the pm2 bit of the mbctrl = 0, this active low output signal is used to select one of two banks of dram as determined by the dram base address register1 (dba1) csr. if pm2 = 1, then the pin is used as brg3/pa12 and may be bidirectional 5.4.4 cas0 - dram column address select bit 0 if the pm3 bit of the mbctrl = 0, this active low output signal is used to enable the dram module upper byte (bits 15?). if pm3 = 1 then the pin is used for pb0/iack7 and may be bidirectional. 5.4.5 cas1 - dram column address select bit 1 if the pm4 bit of the mbctrl = 0, this active low output signal is used to enable the lower byte (bits 7?) of the dram module. if pm4 = 1 then the pin is used for pb1/iack6 and may be bidirectional. 5.4.6 dramrw - dram read/write if the pm5 bit of the mbctrl = 0, this pin is asserted low for a dram write cycle. it is separate from the processor bus r/w signal to allow precharge to take place without regard to the state of r/w . if pm5 = 1 then the pin is used for pb2/iack1 and may be bidirectional. signal descriptions 5-8 mc68en302 reference manual motorola 5.4.7 a0 a new signal, a0 has been added for supporting dynamic bus sizing. this signal replaces the mc68302 a0 that was multiplexed onto uds . a0 is bidirectional. the a0 signal appears on the pin if the pm6 bit of the mbctrl = 0. if pm6= 1 then the pin is used as tout1 /pb4. 5.4.8 wel - write enable for byte 1 (bit 7?it 0) if the pm7 bit of the mbctrl = 1, then the active low signal wel is enabled. if pm7 = 0, then the pin is used for dreq /pa13 and is bidirectional. 5.4.9 weh - write enable for byte 0 (bit 15?it 8) if the pm8 bit of the mbctrl = 1, the active low weh signal appears on the pin. if pm8 = 0, then the pin is used for dack /pa14 and is bidirectional. 5.4.10 oe - output enable output - asserted low, pin is bidirectional. if the pm9 bit of the mbctrl = 0, the active low oe signal is enabled. if pm9 = 1 then the pin is used for done /pa15 and may be bidirectional. 5.5 mc68en302 only pin/signals tena tx tclk rena rx rclk clsn parity0/discpu parity1/busw p aritye /threes tms tck trst tdo tdi gnd 5.5.1 gnd for proper implementation of the en302, this pin must be tied to ground. 5.5.2 trst - jtag reset signal for normal operation the asynchronous trst signal must be held low during system reset. this pin has an internal pullup resistor. signal descriptions motorola mc68en302 reference manual 5-9 5.5.3 tms - jtag test mode select this input controls test mode operation for the en302 test logic as defined by the ieee 1149.1 standard. this pin has an internal pullup resistor. 5.5.4 tdo - jtag test data out this output is used in shifting serial test instructions and test data for on-board test logic defined by the ieee 1149.1 standard. 5.5.5 tdi - jtag test data in this input is used for shiftng serial test instructions and test data for on-board test logic defined by the ieee 1149.1 standard. this pin has an internal pullup resistor. 5.5.6 tck- jtag clock the jtag clock runs at a frequency no greater than 10 mhz. 5.5.7 gnd must be tied to gnd in normal operation.tx ethernet mac transmit data output. 5.5.8 tena ethernet mac transmit data valid output. 5.5.9 tclk ethernet transmit clock input must be 10 mhz +/- 100 ppm according to the 802.3 spec. 5.5.10 rclk ethernet receive clock input. 5.5.11 rx ethernet mac receive data input. 5.5.12 rena this input indicates that the ethernet mac receive data is valid. 5.5.13 clsn this input pin indicates a collision (or sqe test) was detected in the ethernet physical layer. 5.5.14 parity0/discpu parity is controlled by the pcsr register in the module bus controller. this bidirectional pin provides even or odd parity for byte 0 (bit 15?it 8) when not in the reset state. signal descriptions 5-10 mc68en302 reference manual motorola the mc68en302 discpu state is sampled during hardware reset just as in the mc68302. the m68000 core is disabled by asserting the discpu pin high during total system reset. 5.5.15 parity1/busw parity is controlled by the pcsr register in the module bus controller. this bidirectional pin provides even or odd parity for byte 1 (bit 7?it 0) when not in the reset state. the state of busw is sampled during total system reset. when the busw is low during hardware reset, it does not put the 68000 into 68008 mode with an 8 bit bus. instead, having the busw low during hardware reset will force the four en8 bits in the cser registers to one, enabling support for dynamic bus sizing in the chip selects. note that because the 68000 core is in normal 16 bit mode, if the 68000 accesses memory outside of the four chip select areas, it always performs a normal 16 bit access. 5.5.16 paritye /threestate during normal operation, this bidirectional pin is the active low paritye (parity error) output, and is asserted whenever one of the ped (parity error dram) bits in the pcsr is asserted. if this pin is low during total system reset, all bidirectional pins and output pins will be put into three-state mode. this is intended for chip test purposes. 5.6 dram controller i/o 5.6.1 control signal pins the en302 contains 8 dram specific signal pins: cas1 ?as0 , ras1 ?as0 , amux , and dramrw . 5.6.2 column address strobes (cas1 ?as0 ) these active low pins allow seamless interface to column address strobe (cas ) inputs on industry standard dram, providing cas for both bank 0 and bank 1 of the dram controller. two strobes support byte operations on the external 16-bit bus. cas0 corresponds to data pins d15-d8. cas1 corresponds to data pins d7?0. 5.6.3 row address strobes (ras1 ?as0 ) these active low pins allow seamless interface to row address strobe (ras ) inputs on industry standard dram, providing ras for both bytes of a given dram bank. a particular bank corresponds to specific base address and control information programmed in the mc68en302 dram control registers (see 3.2 memory map for a description). ras0 corresponds to bank 0 and ras1 corresponds to bank 1. 5.6.4 dram read/write (dramrw ) this active low pin is asserted to signify that a dram write cycle is occurring. it is separate from the processor bus r/w so that precharge takes place without regard to the state of r/ w . signal descriptions 5-11 mc68en302 reference manual motorola 5.6.5 address mux (amux ) the amux pin is provided for implementing external address muxing circuitry so that external masters may access dram modules controlled by the mc68en302 dram controller. external address muxing must take place in this situation since an access to the mc68en302 as a slave always results in the addresses driven as an input, and does not output addresses to the dram module. another use for the amux pin would be implementations in which a linear dram space is required. 5.6.6 parity (parity1?arity0) these two pins are provided to support parity checking of dram. if enabled, parity is generated on writes and checked on reads. a parity error on a read generates a bus error. parity0 is used in connection with d15-d8 and parity1 is used in connection with d7 d0. parity checking/generation is not supported for external bus masters. 5.6.7 muxing scheme to provide a simplified implementation of the address mux, a unique muxing scheme is provided. rather than providing programmability to change which addresses are muxed on a particular signal, a generic muxing scheme is provided so that one muxing scheme may be utilized by all supported dram bank sizes. table 5-3 shows the dram muxing scheme. the usage listed in the table is for typical operation. it is possible that some users may utilize the base address registers and the mask bits in a non-standard way. table 5-3. address muxing scheme processor address row address column address usage a9 9 1 used for all bank sizes a10 10 2 a11 11 3 a12 12 4 a13 13 5 a14 14 6 a15 15 7 a16 16 8 a18 18 17 used for 512k and up a20 20 19 used for 2m and up a22 22 21 used for 8m signal descriptions 5-12 mc68en302 reference manual motorola motorola mc68en302 reference manual 6-1 section 6 applications 6.1 bringing the mc68en302 out of reset the following paragraphs provide an example of how to bring the mc68en302 out of reset and initialize the ethernet controller to perform internal loopback of one frame. bank 0 of dram is used as packet memory. 1. write the base address register (bar) with the desired starting point of the 302 core 4k-byte relocatable address space. write the module bus controller base address register (mobar) with the starting point of the 4k-byte relocatable address space for the module bus controller, dram controller and ethernet controller csrs and memory. 2. write to the option register (or) to include 256k bytes of space and so that the dtack field may be written to to change the number of wait states. also note that to access data in the program rom, the cfc bits should be modified. 3. or1 affects the ram range, controls dtack , and will also affect whether or not function code comparisons are performed. 4. br1 will set up the ram address, enable the ram, and set the function code appropriately. 5. switch from rom location to dual-port ram location to assure that the reset vector is supplied by the rom, but the exception vectors all come from the ram. this switch is performed by a short, dual-port ram program which is summarized below, and is explained in depth in appendix d.2 of the mc68302 user? manual. move.w #$a001, (address of br1).l move.w #$c201, (address or br0).l jmp ($address in rom).l after the code is copied, then execute the following instruction, which will cause a jump to dual port ram jmp ($base address).l 6. mbc - the mbc register controls bits for overall system level functionality of the module bus controller. this register must be initialized to assure smooth functionality between the sim module on the mc68en302 and the sim module on the internal 302 core. in the mbc register the module bus controller response to bclr from the internal 302 is controlled, as is the parity, function code for the ethernet specific core, applications 6-2 mc68en302 reference manual motorola and the pin muxing that is used in the current mc68en302 application. example: write $5400 to mbc (mfc = 5, ppe = 1). 7. ier - the interrupt extension register replaces the mod, et7, et6 and et1 bits in the 302 gimr. the user must assure that the corresponding bits in the gimr of the internal 302 are all written as zeros for proper functionality of the mc68en302 . the ier is reset to $0000 which configures the interrupt input pins as ipl2 ?pl0 and sets the module bus controller interrupt to level 5. 8. cser0?ser3. the mc68en302 extends the functionality of that provided by the internal 302 core chip selects through the programming of this register. additional functionality includes 8-bit bus operation as well as parity checking and generation. 9. pcsr - this register controls parity operation on the mc68en302. also, bits 9-8 show the result of parity on the current dram bank. 10. dram controller initialization. assume bank 0 is to be used, parity enabled, 0 wait states. dram configuration register (dcr) = $0501 (enable refresh and parity in bank 0, allow supervisor or user access) dram refresh register (drfrsh) = $0000 (refresh every 4096 system clocks) dram base address registers dba0 = desired dram base address and size, bit 0 = 1 dba1 = $0000 (reset value) to ensure correct parity, write $0000 to each memory location used before running other code. 11. ethernet controller initialization. in this example the ethernet controller is initialized to perform internal loopback of one frame. the received frame buffer will be 4 bytes longer than the transmit buffer due to the crc being appended by hardware. ecntrl = $0001 (release reset to the ethernet controller) edma = $000b wmrk = 01 (16 bytes) blim = 011 (max dma burst length of 8 bus transactions (16 bytes of data)) emrblr = $0600 (1536 bytes, this allows receiving a max size frame into a single buffer). ivec = $0140 vg = 1 (bit 1?it 0 of the interrupt vector will be modified). inv7?nv0 = 40 intr_mask = $07bc (all interrupts enabled except backoffdone, transmitbuffer and receivebuffer). ecnfig = $0001 (enable internal loopback). ether_test = $0000 applications motorola mc68en302 reference manual 6-3 ar_cntrl = $7000 hash_en = 0 (all 64 entries used for ?atch?mode) index_en = 1 (enables hardware to write ?eason?and ?rindex?fields into the receive bd. mult1?ult0 = 11 (reject multicast and broadcast frames). place the frame to be looped internally into memory. entire frame should be in a single buffer. allocate receive buffer memory to receive same frame plus 4 crc bytes. initialize cam (arbitrarily select 1 of 64 entries to contain the da of the frame to be transmitted). cam is in perfect match mode. cam starts at moba + $a00. write $ff_ff_ff into all cam entries except 1 write da of transmit frame into remaining entry initialize buffer descriptors. a good practice would be to initialize all locations to $0000 before putting in any specific values. moba + c48 = $0000 (clear e bit in second receive bd) moba + c46 = $llll (a15?0 pointer to receive buffer) moba + c44 = $00hh (a23?16 pointer to receive buffer) moba + c40 = $8000 (set e bit in first receive bd) moba + c08 = $0000 (clear r bit in second transmit bd) moba + c06 = $llll (a15?0 pointer to transmit buffer) moba + c04 = $00hh (a23?16 pointer to transmit buffer) moba + c02 = $0nnn (transmit buffer length) moba + c00 = $8c00 (single buffer frame, hardware appends crc) ecntrl = $0003 (assert ether_en to the ethernet controller, this will cause the buffer descriptor and dma state machines to start operation) frame loopback should occur under hardware control. the tfint and rfint interrupts should occur. once these interrupts have occurred, frame loopback can be verified by the following: receive buffer should contain frame transmitted plus 4 byte crc transmit buffer descriptor should contain the following: moba + c00 = 0c00 moba + c02, c04, c06 locations should be unchanged receive buffer descriptor should contain the following: moba + c40 = $0c00 moba + c42 = value in (moba + c02) + 4 moba + c44, c46 locations should be unchanged 6.2 moving a quicc ethernet driver to a 68en302 ethernet driver porting an ethernet driver written for the mc68360 quicc to the mc68en302 requires only that the quicc driver be pared down to support a simpler implementation of ethernet. in the case of register settings and counters, many of the functions requiring user initialization by the quicc are either supported directly in the mc68en302 hardware as dictated by the ethernet standard, or are provided in the indications that accompany the buffer descriptors. this simplifies the initialization routines in the area of crc calculation as well as the maximum and minimum frame lengths, dma operations and the backoff counter applications 6-4 mc68en302 reference manual motorola operations.the mc68en302 buffer descriptors are a superset of the quicc buffer descriptors. the transmit buffer descriptors are identical, while the mc68en302 receive buffer descriptors include an additional bit in the most significant word which is used as an indication for address matching while running in promiscuous mode. any driver that implements ethernet on the quicc will be able to utilize the same buffer descriptor structure and handling when running on the mc68en302. following the ethernet register map from the mc68360um/ad revision 2.0 user's manual in the table listing the ethernet specific parameters (in the parameter ram), the corresponding function in the mc68en302 is listed below. items in italics indicate that that particular parameter was not part of the quicc initialization process and is not required for crc. the standard 32 bit crc calculation for the crc is performed in the mc68en302 hardware, and therefore there is no need to write to the crc value. 6.2.1 c_pres, c_mask: the quicc preset and mask options for the crc calculation are not required in the mc68en302 because the crc is automatically calculated in hardware. 6.2.2 crcec: in the mc68en302, crc errors are flagged in the buffer descriptor indication rather than keeping a running counter as in the quicc. a software counter may be implemented to support this function with very little difficulty by incrementing the count each time the cr bit (bit 2 in the most significant long word of the buffer descriptor) is set. 6.2.3 alec: the alignment error is flagged in the buffer descriptor indication and therefore a software counter may be implemented to support this function. a counter may be incremented each time the no bit (bit 4 in the most significant long word of the buffer descriptor) is set. 6.2.4 disfc: this function is not required in standard ethernet. if frames are discarded because of error conditions, then the buffer descriptor is flagged with the error notification. if a buffer descriptor is not available, then an overrun error occurs, notifying the user that a frame was discarded because no buffer descriptors were available. if a frame is discarded because of the address filtering that is implemented on the mc68en302, there is no indication provided since this function is generally used for collecting network statistics and does not add to the station performance. 6.2.5 pads: in the transmit direction the padding is automatic and is always generated as all ones. 6.2.6 ret_lim: set in hardware to standard ethernet values of 15. applications motorola mc68en302 reference manual 6-5 6.2.7 ret_cnt: the rc field in the transmit buffer descriptor is the retry count (bits 5-2 of the most significant long word). if the rl bit is also set (bit 6) then the rc bits have no meaning since the retry limit has been exceeded. 6.2.8 mflr: the maximum frame length is set in mc68en302 hardware to 1518. 6.2.9 minflr: the minimum frame length is set in mc68en302 hardware to 64. 6.2.10 maxd1, maxd2: these operations are covered by the maximum frame length being automatically set at 1518 bytes. this is not programmable in the mc68en302. 6.2.11 max_b: the mc68en302 supports buffer descriptor options ranging from 8 tx and 120 rx buffer descriptors to 64 tx and 64 rx buffer descriptors. 6.2.12 gaddr1-4 / paddr_hml / iaddr1-4: ar_cntl provides the address filtering. options in the mc68en302 are either 64 perfect address matches or 62 perfect address matches with address filtering via a hash routine. 6.2.13 p_per: the persistance is not programmable on the mc68en302 but rather is a specific value set in the mc68en302 hardware. 6.2.14 rfbd_ptr/tfbd_ptr/tlbd_ptr: buffer descriptors in the mc68en302 are placed at mobar+$c00 through mobar+$fff. the tfbd_ptr is always at mobar+$c00. the tlbd_ptr can range from mobar+$c00 in a one buffer frame to mobar+$dff in a 64 transmit buffer frame. the rfbd_ptr is either at mobar+$c40, mobar+$c80, mobar+$d00 or mobar+$e00 depending on the setting of the bdsize bits. 6.2.15 tx_len: the tx frame length counter is part of the data length field in the buffer descriptor. to come up with the total tx frame length the user must keep track of the data length in the buffer descriptors belonging to that frame. applications 6-6 mc68en302 reference manual motorola 6.2.16 boff_cnt: the backoff count is set to a specific value in the mc68en302 hardware. 6.2.17 taddr_h/m/l: implemented in the 64 entry address recognition table as per user set up. 6.2.18 gsmr (quicc section 7.10.2) the following table represents bits relating to ethernet in the quicc? gsmr register and indicate the corresponding function on the mc68en302. bit(s) mnemonic function on mc68en302 47/46 tcrc hardware function 37 rfw set width in hardware 28 tci clocking optimized in hardware 23-21 tpl preamble set to 6 bytes in hardware 20 tpp preamble pattern defined as 10 3-0 mode ethernet only motorola mc68360 user? manual 7-1 section 7 ieee 1149.1 (jtag) test access port the mc68en302 provides a dedicated user-accessible test access port (tap) that is fully compatible with the ieee 1149.1 standard test access port and boundary scan architec- ture . the tap consists of five dedicated signal pins, a 16-state tap controller, boundary scan and instruction registers. a boundary scan register links i/o pins into a single shift register. the test logic, implemented utilizing static logic design, is independent of the device system logic. the mc68en302 implementation provides the capability to: 1. perform boundary scan operations to test circuit-board electrical continuity. 2. bypass the mc68en302 for a given circuit-board test by effectively reducing the boundary scan register to a single cell. 3. sample the mc68en302 system pins during operation and transparently shift out the result in the boundary scan register. 4. disable the output drive to pins during circuit-board testing. note certain precautions must be observed to ensure that the ieee 1149.-like test logic does not interfere with nontest operation. see 7.6 non-scan chain operation for details. in addition to the scan-test logic, the mc68en302 contains a signal that can be used to three-state all mc68en302 output signals. this signal, called three-state (threestate ), is sampled during system reset. 7.1 overview an overview of the mc68en302 scan chain implementation is shown in figure 7-1. the mc68en302 implementation includes a tap controller, a 4-bit instruction register, and two test registers (a 1-bit bypass register and a 163-bit boundary scan register). this implemen- tation includes a dedicated tap consisting of the following signals: tck? test clock input to synchronize the test logic. tms? test mode select input (with an internal pullup resistor) that is sampled on the rising edge of tck to sequence the tap controller? state machine. tdi? test data input (with an internal pullup resistor) that is sampled on the rising edge of tck. ieee 1149.1 (jtag) test access port 7-2 motorola tdo? three-stateable test data output that is actively driven in the shift-ir and shift- dr controller states. tdo changes on the falling edge of tck. trst ?n asynchronous reset (with an internal pullup resistor) that provides initializa- tion of the tap controller and other logic required by the standard. figure 7-1. test logic block diagram 7.2 tap controller the tap controller is responsible for interpreting the sequence of logical values on the tms signal. it is a synchronous state machine that controls the operation of the jtag logic. the state machine is shown in figure 7-2. the value shown adjacent to each arc represents the value of the tms signal sampled on the rising edge of the tck signal. for a description of the tap controller states, refer to the ieee 1149.1 document. boundary scan register bypass decoder tdo tdi tms tck trst 0 1 2 0 195 m u x m u x 3-bit instruction register tap ctlr ieee 1149.1 (jtag) test access port motorola 7-3 figure 7-2. tap controller state machine 7.3 boundary scan register the mc68en302 ieee 1149.1 implementation has a 163-bit boundary scan register. this register contains bits for all device signal pins and associated control signals with the follow- ing exceptions. the frz and iac signals which are not pinned out on the tqfp package are not included in the scan chain. the xtal pin is associated with an analog signal and is not included in the boundary scan register. the extal pin (clock in) is not included to min- imize loading on this signal, however a boundary scan cell is included for an internal signal, sclk which is the clock input to the mbc, ethernet and dram controller logic. test logic reset run-test/idle select-dr_scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr select-ir_scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 1 1 ieee 1149.1 (jtag) test access port 7-4 motorola all mc68en302 bidirectional pins have a single register bit in the boundary scan register for pin data and are controlled by an associated control bit in this register. fifty bits in the bound- ary scan register define the output enable signal for associated groups of bidirectional and three-stateable output pins. the control bits and their bit positions are listed in table 7-1. the boundary scan bit definitions are listed in table 7-2. the first column in the table defines the bit? ordinal position in the boundary scan register. the shift register cell nearest tdo (i.e., first to be shifted out) is defined as bit 0; the last bit to be shifted out is 162. the second column references one of the seven mc68en302 cell types depicted in figure 7-3 through figure 7-9, which describe the cell structure for each type. the third column lists the pin name for all pin-related cells or defines the name of bidirec- tional control register bits. the fourth column lists the pin type for convenience, where output indicates a three-state- able output pin, i/o indicates a bidirectional pin and input represents an input. the last column indicates the associated boundary scan register control bit for bidirectional and output pins. bidirectional pins include a single scan cell for data (bicell) as depicted in figure 7-6. these bits are controlled by the cell shown in figure 7-5. the value of the control bit determines whether the bidirectional pin is an input or an output. one or more bidirectional data cells table 7-1. boundary scan control bits name bit number name bit number name bit number out_enb 0 ras1_enb 86 berrb_out 125 drv_ext_a 5 oeb_enb 88 clko_enb 130 drv_ext_d 32 wehb_enb 90 drv_ext_cntl 133 rena_enb 54 welb_enb 92 drv_ext_uds 137 rx_enb 56 paritye_enb 94 cas0_enb 139 pa0_enb 62 parity_enb 96 cas1_enb 141 txd2_enb 64 cd3_enb 101 dram_rw_enb 143 pa2_enb 66 txd1_enb 105 pb3_enb 145 pa3_enb 68 tclk1_enb 107 a0_enb 147 pa4_enb 70 rclk1_enb 109 pb5_enb 149 pa5_enb 72 dtack_enb 111 pb6_enb 151 pa6_enb 74 ecpt_buf 113 wdogb_enb 153 pa8_enb 76 bgack_enb 115 pb8_enb 155 txd3_enb 78 br_enb 117 pb9_enb 157 pa10_enb 80 haltb_out 119 pb10_enb 159 pa11_enb 82 resetb_out 121 pb11_enb 161 ras0_enb 84 avec_enb 123 ieee 1149.1 (jtag) test access port motorola 7-5 can be serially connected to a control cell as shown in figure 7-10. note that, when sampling the bidirectional data cells, the cell data can be interpreted only after examining the io con- trol cell to determine pin direction, and also note that the control cell captures the value of the following cell. ieee 1149.1 (jtag) test access port 7-6 motorola table 7-2. boundary scan bit definition bit num cell type pin/cell name pin type output ctlcell bit num cell type pin/cell name pin type output ctlcell 0 encell out_enb - - 39 bicell d9 i/o drv_ext_d 1 iocell cs3 output out_enb 40 bicell d8 i/o drv_ext_d 2 iocell cs3 output out_enb 41 bicell d7 i/o drv_ext_d 3 iocell cs1 output out_enb 42 bicell d6 i/o drv_ext_d 4 iocell cs0 output out_enb 43 bicell d5 i/o drv_ext_d 5 dicell drv_ext_a - - 44 bicell d4 i/o drv_ext_d 6 bicell fc2 i/o drv_ext_a 45 bicell d3 i/o drv_ext_d 7 bicell fc1 i/o drv_ext_a 46 bicell d2 i/o drv_ext_d 8 bicell fc0 i/o drv_ext_a 47 bicell d1 i/o drv_ext_d 9 bicell a1 i/o drv_ext_a 48 bicell d0 i/o drv_ext_d 10 bicell a2 i/o drv_ext_a 49 iscell tclk input - 11 bicell a3 i/o drv_ext_a 50 iocell tena output out_enb 12 bicell a4 i/o drv_ext_a 51 iscell rclk input - 13 bicell a5 i/o drv_ext_a 52 iscell clsn input - 14 bicell a6 i/o drv_ext_a 53 iocell tx output out_enb 15 bicell a7 i/o drv_ext_a 54 dicell rena_enb - - 16 bicell a8 i/o drv_ext_a 55 bicell rena i/o rena_enb 17 bicell a9 i/o drv_ext_a 56 dicell rx_enb - - 18 bicell a10 i/o drv_ext_a 57 bicell rx i/o rx_enb 19 bicell a11 i/o drv_ext_a 58 iscell cts3 input - 20 bicell a12 i/o drv_ext_a 59 iscell cd1 input - 21 bicell a13 i/o drv_ext_a 60 iscell cts1 input - 22 bicell a14 i/o drv_ext_a 61 iscell rxd1 input - 23 bicell a15 i/o drv_ext_a 62 dicell pa0_enb - - 24 bicell a16 i/o drv_ext_a 63 bicell rxd2 i/o pa0_enb 25 bicell a17 i/o drv_ext_a 64 dicell txd2_enb - - 26 bicell a18 i/o drv_ext_a 65 bicell txd2 i/o txd2_enb 27 bicell a19 i/o drv_ext_a 66 dicell pa2_enb - - 28 bicell a20 i/o drv_ext_a 67 bicell rclk2 i/o pa2_enb 29 bicell a21 i/o drv_ext_a 68 dicell pa3_enb - - 30 bicell a22 i/o drv_ext_a 69 bicell tclk2 i/o pa3_enb 31 bicell a23 i/o drv_ext_a 70 dicell pa4_enb - - 32 dicell drv_ext_d - - 71 bicell cts2 i/o pa4_enb 33 bicell d15 i/o drv_ext_d 72 dicell pa5_enb - - 34 bicell d14 i/o drv_ext_d 73 bicell rts2 i/o pa5_enb 35 bicell d13 i/o drv_ext_d 74 dicell pa6_enb - - 36 bicell d12 i/o drv_ext_d 75 bicell cd2 i/o pa6_enb 37 bicell d11 i/o drv_ext_d 76 dicell pa8_enb - - 38 bicell d10 i/o drv_ext_d 77 bicell rxd3 i/o pa8_enb ieee 1149.1 (jtag) test access port motorola 7-7 78 dicell txd3_enb - - 118 bicell br i/o br_enb 79 bicell txd3 i/o txd3_enb 119 dicell haltb_out - - 80 dicell pa10_enb - - 120 bicell halt i/o haltb_ou 81 bicell rclk3 i/o pa10_enb 121 dicell resetb_out - - 82 dicell pa11_enb - - 122 bicell reset i/o resetb_out 83 bicell tclk3 i/o pa11_enb 123 dicell avec_enb - - 84 dicell ras0_enb - - 124 bicell avec i/o avec_enb 85 bicell ras0 i/o ras0_enb 125 dicell berrb_out - - 86 dicell ras1_enb - - 126 bicell berr i/o berrb_out 87 bicell ras1 i/o ras1_enb 127 iscell ipl2 input - 88 dicell oeb_enb - - 128 iscell ipl1 input - 89 bicell oe i/o oeb_enb 129 iscell ipl0 input - 90 dicell wehb_enb - - 130 clko_encell clko_enb - - 91 bicell weh i/o wehb_enb 131 iocell clko output clko_enb 92 dicell welb_enb - - 132 iscell sclk (1) 1 input - 93 bicell wel i/o welb_enb 133 dicell drv_ext_cntl -- 94 dicell paritye_enb - - 134 bicell rw i/o drv_ext_cntl 95 bicell paritye i/o paritye_enb 135 bicell as i/o drv_ext_cntl 96 dicell parity_enb - - 136 bicell lds i/o drv_ext_cntl 97 bicell parity0 i/o parity_enb 137 dicell drv_ext_uds -- 98 bicell parity1 i/o parity_enb 138 bicell uds i/o drv_ext_uds 99 iscell test302 input - 139 dicell cas0_enb - - 100 iocell amux output out_enb 140 bicell cas0 i/o cas0_enb 101 dicell cd3_enb - - 141 dicell cas1_enb - - 102 bicell cd3 i/o cd3_enb 142 bicell cas1 i/o cas1_enb 103 iocell rts3 output out_enb 143 dicell dram_rw_enb -- 104 iocell rts1 output out_enb 144 bicell dramrw i/o dram_rw_enb 105 encello txd1_enb - - 145 dicell pb3_enb - - 106 iocell txd1 output txd1_enb 146 bicell tin1 i/o pb3_enb 107 dicell tclk1_enb - - 147 dicell a0_enb - - 108 bicell tclk1 i/o tclk1_enb 148 bicell a0 i/o a0_enb 109 dicell rclk1_enb - - 149 dicell pb5_enb - - 110 bicell rclk1 i/o rclk1_enb 150 bicell tin2 i/o pb5_enb 111 dicell dtack_enb - - 151 dicell pb6_enb - - 112 bicell dtack i/o dtack_enb 152 bicell tout2 i/o pb6_enb 113 dicell ecpt_buf - - 153 dicell wdogb_enb -- 114 bicell bg i/o ecpt_buf 154 bicell wdog i/o wdogb_enb 115 dicell bgack_enb - - 155 dicell pb8_enb - - 116 bicell bgack i/o bgack_enb 156 bicell pb8 i/o pb8_enb 117 dicell br_enb - - 157 dicell pb9_enb - - table 7-2. boundary scan bit definition ieee 1149.1 (jtag) test access port 7-8 motorola notes: 1. boundary scan cell for sclk (bit number 132 in table) is for the internal sclk signal used in the ethernet controller. a boundary scan cell was not included on the extal clock input signal to minimize loading. figure 7-3. output latch cell (iocell) figure 7-4. input pin cell (iscell) 158 bicell pb9 i/o pb9_enb 161 dicell pb11_enb - - 159 dicell pb10_enb - - 162 bicell pb11 i/o pb11_enb 160 bicell pb10 i/o pb10_enb table 7-2. boundary scan bit definition 1 1 mux g1 1 1 mux g1 c d c d from last cell clock dr update dr shift dr 1?xtest / clamp data from to output buffer 0?therwise logic system to next cell from last cell 1 mux 1 g1 to device log ic input pin shift dr clock dr 1d c1 to next cell ieee 1149.1 (jtag) test access port motorola 7-9 figure 7-5. control cell (dicell) figure 7-6. bidirectional cell (bicell) 1 mux 1 g1 1 mux 1 g1 output contro l fro m syste m log ic from last cell 1d c1 clock dr 1d c1 update dr to next cell to output d irection 1 ?extest 0 ?otherwise shift dr hi_z 1 1 mux g1 1 1 mux g1 c d c d to next cell from 1?xtest / clamp to output driver 0?ample from last cell clock dr update dr direction 1 1 mux g1 from i/o pin shift dr from io en ctl data from system logic 1 1 mux g1 1?xtest / clamp 0?therwise i/o pin control cell output control from system logic mode ieee 1149.1 (jtag) test access port 7-10 motorola figure 7-7. output enable cell (encell) figure 7-8. output enable cell (encello) 1 1 mux g1 1 1 mux g1 c d c d from last cell clock dr update dr shift dr 1?xtest / clamp to output buffer 0?therwise t hree-state to next cell hi-z 1 1 mux g1 1 1 mux g1 c d c d from last cell clock dr update dr shift dr 1?xtest / clamp to output buffer 0?therwise to next cell hi-z three-state data from system logic ieee 1149.1 (jtag) test access port motorola 7-11 figure 7-9. output enable cell (clko_encell) 1 1 mux g1 1 1 mux g1 c d c d from last cell clock dr update dr shift dr 1?xtest / clamp to output buffer 0?therwise three-state to next cell hi-z b clkomod1 clkomod2 a b a b a clkoenb16_s clkoenb24_s ieee 1149.1 (jtag) test access port 7-12 motorola figure 7-10. general arrangement for bidirectional pins 7.4 instruction register the mc68en302 ieee 1149.1 implementation includes the three mandatory public instruc- tions (extest, sample/preload, and bypass), and also supports the clamp instruc- tion. one additional public instruction (hi-z) provides the capability for disabling all device output drivers. the mc68en302 includes a 4-bit instruction register without parity. data is transferred from the shift register to the parallel outputs during the update-ir controller state. the four bits used to decode the instructions are listed in table 7-3. the parallel output of the instruction register logic is reset to the equivalent to the bypass instruction. during the capture-ir controller state, the parallel inputs to the instruction shift register are loaded with 0001. table 7-3. instruction decoding code ir[3] ir[2] ir[1] ir[0] instruction 0000 extest 0010 sample/preload 1111 bypass 1001 hi-z 1100 clamp all other cases bypass i/o pin note: more than one io.cell could be serially connected and controlled by a single io.ctl. * from last cell output data input data enable from direction ctl system logic io cell ieee 1149.1 (jtag) test access port motorola 7-13 7.4.1 extest the external test (extest) instruction selects the 163-bit boundary scan register. by using the tap, the register is capable of a) scanning user-defined values into the output buffers, b) capturing values presented to input pins, c) controlling the direction of bidirec- tional pins, and d) controlling the output drive of three-stateable output pins. for more details on the function and use of extest, refer to the ieee 1149.1 document. 7.4.2 sample/preload the sample/preload instruction provides two separate functions. first, it provides a means to obtain a snapshot of system data and control signals. the snapshot occurs on the rising edge of tck in the capture-dr controller state. the data can be observed by shifting it transparently through the boundary scan register. note since there is no internal synchronization between the scan chain clock (tck) and the system clock (clko), the user must provide some form of external synchronization to achieve mean- ingful results. the second function of sample/preload is to initialize the boundary scan register output cells prior to selection of extest. this initialization ensures that known data will appear on the outputs when entering the extest instruction. 7.4.3 bypass the bypass instruction selects the single-bit bypass register as shown in figure 7-11. this creates a shift register path from tdi to the bypass register and, finally, to tdo, circumvent- ing the 163-bit boundary scan register. this instruction is used to enhance test efficiency when a component other than the mc68en302 becomes the device under test. figure 7-11. bypass register when the bypass register is selected by the current instruction, the shift register stage is set to a logic zero on the rising edge of tck in the capture-dr controller state. therefore, the first bit to be shifted out after selecting the bypass register will always be a logic zero. 1 1 mux g1 c d to tdo from tdi 0 shift dr ieee 1149.1 (jtag) test access port 7-14 motorola 7.4.4 clamp the clamp instruction selects the single-bit bypass register as shown in figure 7-11, and the state of all signals driven from system output pins is completely defined by the data pre- viously shifted into the boundary scan register (for example, using the sample/preload instruction). 7.4.5 hi-z the hi-z instruction is provided as a manufacturer? optional public instruction to prevent having to backdrive the output pins during circuit-board testing. when hi-z is invoked, all output drivers are turned off (i.e., high impedance). the instruction selects the bypass reg- ister. note on the mc68en302, the threestate pin may also be used during system reset to perform the same function. 7.5 mc68en302 restrictions the control afforded by the output enable signals using the boundary scan register and the extest instruction requires a compatible circuit-board test environment to avoid device- destructive configurations. the user must avoid situations in which the mc68en302 output drivers are enabled into actively driven networks. 7.6 non-scan chain operation in non-scan chain operation, there are two constraints. first, the tck input does not include an internal pullup resistor and should not be left unconnected to preclude mid-level inputs. the second constraint is to ensure that the scan chain test logic is kept transparent to the system logic by forcing tap into the test-logic-reset controller state. this is accomplished by asserting the trst signal during system reset (reset and halt asserted) and leaving tms unconnected or tied to vcc. motorola mc68en302 reference manual 8-1 section 8 mc68en302 electrical characteristics 8.1 power dissipation at 25 mhz, typical current will be 140 ma (with all circuitry active), max current will be tbd. 8.2 changes to existing mc68302 timing specs the timing for the mc68en302 signals that are shared with the mc68302 are the same as specified in the mc68302 manual. mc68en302 electrical characteristics 8-2 mc68en302 reference manual motorola 8.3 dram interface timing any spec numbers shown in diagrams and not listed in the table are unchanged from the mc68302 user? manual. notes: 1. width increases by clock period (tcyc) for each wait state added. 2. width increases by clock period (tcyc) for each increase in p1?0 (ras precharge time). 3. parity enabled timing (spec 27a) only applies to bank(s) which have parity enabled. table 8-1. dram interface timing num characteristic symbol 20 mhz 25 mhz unit min max min max 6a clko low to column address valid 0 25 0 25 9 clko high to as , rasx asserted 3 25 3 20 ns 9a clko high to rasx deasserted 3 25 3 20 ns 400 rasx asserted to row address invalid 12 - 12 - ns 401 rasx asserted to column address valid 15 - 15 - ns 402 rasx width asserted (1) 85 - 75 - ns 403 rasx width negated (2) 85 - 75 - ns 404 rasx asserted to cas asserted 35 - 35 - ns 405 clko high to casx asserted 3 25 3 20 ns 405a clko high to casx asserted (refresh) 3 25 3 20 ns 406 clko high to casx negated 3 25 3 20 ns 407 column address valid to casx asserted 15 - 15 - ns 408 casx asserted to column address negated 50 - 40 - ns 409 casx asserted to rasx negated 35 - 30 - ns 410 casx width asserted (1) 75 - 60 - ns 411 casx width negated (2) 75 - 60 - ns 412 casx negated to data, parity-in invalid 0-0-ns 415 dramrw low to casx asserted 30 - 25 - ns 416 casx asserted to dramrw high 100 - 80 - ns 417 data-out valid to casx asserted 15 - 10 - ns 417a parity-out valid to casx asserted 0-0-ns 418 cas asserted to data/parity-out invalid (1) 100 - 80 - ns 419 clko low to amux negated 3 15 3 15 ns 420 clko low to amux asserted 3 15 3 15 ns 421 amux high to rasx asserted 50 - 40 - ns 422 rasx asserted to amux low 10 - 10 - ns 423 amux low to cas asserted 15 - 15 - ns 424 casx asserted to amux high 55 - 45 - ns 23 clko low to data out valid - 25 - 20 ns 23a clko low to parity out valid - 40 - 33 ns 27 data-in to clko low (parity disabled) (3) 6-5-ns 27a data/parity-in to clko low (parity enabled) (3) 16 - 12 - ns 425 clko high to paritye valid - 15 - 15 ns mc68en302 electrical characteristics motorola mc68en302 reference manual 8-3 clk0 (output) a23?0 (output) as (output) rasx (output) casx (output) dramrw (output) amux (output) data15 data0 (input, pex=0) data/parity (input, pex=1) paritye (output) figure 8-1. dram read cycle s0 s1 s2 s3 s4 s5 s6 s7 402 409 403 404 405 406 400 401 407 9 408 410 411 412 420 422 419 421 423 424 27 27a 9a 6 6a 425 8 mc68en302 electrical characteristics 8-4 mc68en302 reference manual motorola clk0 (output) a23?0 (output) as (output) rasx (output) casx (output) dramrw (output) amux (output) data15 data0 (output) parity1/0 (output) figure 8-2. dram write cycle s0 s1 s2 s3 s4 s5 s6 s7 402 409 403 404 405 406 400 401 407 9 408 410 411 420 422 419 421 423 424 23 23a 415 416 417 417a 418 9a 6 6a 8 mc68en302 electrical characteristics motorola mc68en302 reference manual 8-5 s0 s1 s2 s3 s4 s5 s6 s7 9a 405a 6 9 406 clk0 (output) a23?0 (output) as (output) rasx (output) casx (output) dramrw (output) figure 8-3. dram refresh 8.4 ethernet timing 1. notes: 1. txd, tena are actually driven by tclk low (falling) edge. max delay from tclk low to txd, tena change is 20 nsec. table 8-2. ethernet timing num characteristic symbol min max unit 520 clsn width high 105 ns 521 rclk rise/fall time 15 ns 522 rclk width low 40 60 ns 523 rclk period 80 120 ns 524 rx, rena setup to rclk rising edge 25 ns 525 rx hold time from rclk rising edge 0 ns 526 rena active delay (from rclk rising edge of the last data bit) 0ns 527 rena width low 105 ns 528 tclk rise/fall time 15 ns 529 tclk width low 45 55 ns 530 tclk clock period 99 101 ns 531 tclk high to txd, tena active delay (1) 45 75 ns 532 tclk high to txd, tena inactive delay (1) 45 75 ns 8 mc68en302 electrical characteristics 8-6 mc68en302 reference manual motorola 522 521 521 523 524 525 526 527 clsn (input) figure 8-4. ethernet collision timing rclk (input) rx (input) rena (input) figure 8-5. ethernet receive timing tclk (input) tx (output) tena (output) figure 8-6. ethernet transmit timing 520 531 528 528 529 530 532 mc68en302 electrical characteristics motorola mc68en302 reference manual 8-7 8.5 jtag interface timing the tck, trst , tms, tdi, tdo are new signals added to the mc68en302 that do not exist on the mc68302. figure 8-7. test clock input timing diagram figure 8-8. trst timing diagram num characteristic min max unit tck frequency of operation 0 10 mhz 1 tck cycle time in crystal mode 100 ns 2 tck clock pulse width measured at 1.5 v 40 ns 3 tck rise and fall times 0 3 ns 6 boundary scan input data setup time 10 ns 7 boundary scan input data hold time 18 ns 8 tck low to output data valid 0 30 ns 9 tck low to output high impedance 0 40 ns 10 tms, tdi data setup time 10 ns 11 tms, tdi data hold time 10 ns 12 tck low to tdo data valid 0 20 ns 13 tck low to tdo high impedance 0 20 ns 14 trst assert time 100 ns 15 trst setup time to tck low 40 ns v v tck 1 2 2 3 3 vm vm ih il (input) tck trst (input) (input) 15 14 mc68en302 electrical characteristics 8-8 mc68en302 reference manual motorola figure 8-9. boundary scan (jtag) timing diagram figure 8-10. test access port timing diagram tck v v data outputs data inputs output data valid data outputs output data valid data outputs il ih input data valid 67 8 9 8 (input) tck v v data outputs data inputs output data valid data outputs output data valid data outputs il ih input data valid 67 8 9 8 (input) mc68en302 electrical characteristics motorola mc68en302 reference manual 8-9 8.6 oe , wel , weh timing these are new signals added to the mc68en302 that do not exist on the mc68302. 8.6.1 oe timing during a read, the timing on the oe signal is similar to the mc68302 uds , lds lines (assertion and deassertion reference the same clock edges as uds , lds ). reference figure 6-2 (read cycle timing diagram) in the mc68302 user? manual. the following mc68302 specifications define oe timing: mc68302 spec 9 - clk0 high to oe asserted mc68302 spec 12 - clk0 low to oe negated 8.6.2 wel , weh timing during a write, the timing on the wel , weh signals is similar to the mc68302 uds , lds lines (assertion and deassertion reference the same clock edges as uds , lds ). reference figure 6-3 (write cycle timing diagram) in the mc68302 user? manual. the following mc68302 specifications define wel , weh timing: mc68302 spec 9 - clk0 high to wel , weh asserted mc68302 spec 12 - clk0 low to wel , weh negated mc68en302 electrical characteristics 8-10 mc68en302 reference manual motorola motorola mc68en302 reference manual 9-1 section 9 ordering and mechanical information this section contains the ordering information, pin assignments, and package dimensions for the mc68en302. 9.1 pin assignment ordering and mechanical information 9-2 mc68en302 reference manual motorola 9.1.1 pin grid array (pga) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 a b c d e f g h j k l m n p r 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 a b c d e f g h j k l m n p r mc68en302rc top view vcc gnd txd1 frz gnd gnd paritye wel cts2 gnd gnd tclk2 rclk2 txd2 rxd2 nc amux gnd parity1 parity0 vcc vcc rxd1 cts1 cd1 cts3 rx rena nc tx vcc tclk1 bg dtack weh oe ras1 ras0 txd3 rxd3 vcc vcc cd2 rts2 tclk avec bgack trst rclk1 rts1 rts3 cd3 gnd gnd tclk3 rclk3 nc gnd d0 gnd berr br tck vcc nc gnd d1 d4 vcc ipl2 halt tms vcc clsn d2 d5 vcc ipl1 reset tpad1 gnd rclk d3 d6 d8 dramrw lds xtal_pad clko ipl0 tena gnd d7 d9 nc tin1 uds gnd vcc d10 d12 a20 gnd vcc gnd gnd vcc d11 d13 vcc gnd a0 cas0 as gnd d15 a23 a19 vcc vcc a15 a3 a2 a1 fc0 vcc tin2 cas1 gnd a22 a18 a5 a4 gnd gnd vcc fc1 fc2 cs0 cs1 gnd nc a21 a17 a10 a9 a8 a7 a6 iac tdi tpad2 cs3 cs2 gnd td0 a16 a14 a13 a12 gnd gnd a11 pb11 pb10 pb9 pb8 wdog gnd gnd tout2 vcc gnd rw extal gnd d14 vcc gnd nc nc ordering and mechanical information motorola mc68en302 reference manual 9-3 9.1.2 144 thin quad flat pack (tqfp) 144 1 18 19 36 37 54 55 72 73 90 91 108 109 126 127 a1 a2 a3 a4 gnd a5 a6 a7 a8 a9 a10 a11 gnd a12 a13 a14 a15 vdd a16 a17 a18 a19 gnd a20 a21 a22 a23 vdd gnd d15 d14 d13 d12 gnd d11 d10 d9 d8 vdd d7 d6 d5 d4 gnd d3 d2 d1 d0 tena rclk cd3 rts3 rts1 tx rena rx cts3 cd1 cts1 rxd1 rxd2 txd2 rclk2 tclk2 gnd cts2 rts2 cd2 vdd rxd3 txd3 rclk3 tclk3 gnd ras0 ras1 oe weh wel paritye gnd vdd parity0 parity1 gnd amux vdd a0 tin2 tclk1 txd1 rclk1 vdd gnd trst dtack tck tms bg br bgack halt reset avec berr ipl2 ipl1 clko ipl0 vdd extal xtal r/w gnd as lds uds cas0 gnd cas1 dramrw tin1 gnd tout2 wdog pb8 pb9 pb10 pb11 tdi tdo cs1 cs0 fc2 fc1 vdd fc0 tclk mc68en302 (top view) clsn gnd vdd cs3 cs2 gnd ordering and mechanical information 9-4 mc68en302 reference manual motorola 9.2 package dimensions 9.2.1 pin grid array (pga) case 768e-01 issue o date 04/04/94 ! ! $ ! " v g g v k l c d 145 pl s x t ! # ! pin a1 a b ordering and mechanical information motorola mc68en302 reference manual 9-5 9.2.2 144 thin quad flat pack (tqfp) 0.20 (0.008) l?m n h 0.20 (0.008) l?m n h c l detail "c" k e y dim a millimeters min max inches min max 20.00 bsc 20.00 bsc notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane -h- is located at bottom of lead and coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums -l- , -m- , and -n- to be determined at datum plane -h- . 5. dimensions s and v to be determined at seating plane -t- . 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 (0.010 per side. dimensions a and b do not include mold mismatch and are determined at datum line -h- . 7. dimension d does not include dambar protrusion. allowable dambar protrusion shall not cause the d dimension to exceed 0.35 (0.014). h ? 0.08 (0.003) seating plane detail "c" detail "b" detail "b" base metal 0.08(0.003) t l e m n m m s detail "a" detail "a" (rotated 90?) 144 pl g p case 918-02 144 tqfp b b1 0.790 bsc 22.00 bsc 0.866 bsc 11.00 bsc 0.433 bsc 22.00 bsc 0.866 bsc 11.00 bsc 0.433 bsc 0.790 bsc 10.00 bsc 10.00 bsc 0.25 bsc 0.010 bsc 0.394 bsc 0.394 bsc c d e f j g s s1 v v1 y k p r1 r2 aa 0.50 bsc. 0.20 bsc. z a1 c1 c2 0.002 0.006 0.15 0.05 0.053 0.057 1.45 1.35 0.007 0.011 0.27 0.17 0.018 0.030 0.75 0.45 0.007 0.009 0.23 0.17 0.004 0.008 0.20 0.09 0.005 0.008 0.20 0.13 0.005 0.008 0.20 0.13 0.16 0.09 0.006 0.004 0? 0? 0? 7? 0? 7? 13? 11? 13? 11? 1 2 0.50 ref 0.020 ref 0.25 ref 0.010 ref 1.00 ref 0.039 ref 0.055 0.063 1.60 1.40 r1 gage plane 1 2 r2 c1 c2 0.25 (0.010) c t a s1 a1 s b v1 b1 72 73 108 109 144 1 37 36 d f j aa l, m, n 0.05 (0.005) q q q q q q z v ordering and mechanical information 9-6 mc68en302 reference manual motorola 9.3 standard ordering information package type frequency (mhz) temperature order number thin quad flat pack (tqfp) 20 0 o c-70 o c mc68en302pv20 thin quad flat pack (tqfp) 25 0 o c-70 o c mc68en302pv25 pin grid array (pga) (for development only, not available in production quantity) 25 0 o c-70 o c pc68en302rc25 viii mc68en302 reference manual motorola mc68302 product summary page search motorola : semiconductors : 68k/coldfire? : products : 68k m683xx : mc68302 page contents l features l parametrics l documentation l design tools l orderable parts other info l faqs l literature services l 68k/coldfire? l microcontrollers l networking l powerquicc? communication processors l 3rd party design help mc68302 : integrated multi-protocol processor the mc68302 is a versatile one-chip processor that incorporates the main building blocks needed for the design of a wide variety of networking and communications products. the mc68302 was the first device to offer the benefits of a closely coupled, industry-standard, mc68000/mc68008 microprocessor core and a flexible communications architecture. this multi-channel communications device may be configured to support a number of popular industry-standard interfaces, including those for the integrated services digital network (isdn) basic rate and terminal adapter applications. through a combination of architectural and programmable features, concurrent operation of different protocols is easily achieved using the mc68302. data concentrators, modems, line cards, bridges, and gateways are examples of other suitable applications for this versatile device. the mc68302 is an hcmos device consisting of an mc68000/mc68008 microprocessor core, a system integration block (sib), and a communications processor (cp). this device is still recommended for new designs. link product picture link block diagram mc68302 features product highlights l mc68000/mc68008 microprocessor core l efficient architecture involves a separate risc processor for handling communications l three serial communications controllers (sccs) l support for hdlc/sdlc, bisync, uart, ddcmp, and totally transparent protocols. l two serial management controllers (smcs) for idl and gci channel. l available at 16, 20, 25, and 33 mhz in three different thin quad flat pack packages. l strong 3rd party tools support. typical applications l isdn equipment l data concentrators l modems file:///h|/imaging/bitting/cpl/20021108_2/11072002_10/moto/11072002_html/mc68302.htm (1 of 12) [11/12/02 2:08:15 pm] mc68302 product summary page l line cards l network bridges l gateways technical specifications l mc68000/mc68008 microprocessor core (may be disabled to use the imp as a peripheral) l sib including: m independent direct memory access (idma) controller m interrupt controller with two modes of operation m parallel i/o ports, some with interrupt capability m on-chip 1152-bytes of dual-port ram m three timers, with a software watchdog timer m four programmable chip-select lines with wait-state logic m programmable address mapping of dual-port ram and imp registers l on-chip clock generator with an output clock signal l system control m bus arbitration logic with low interrupt latency support m system control register m hardware watchdog for monitoring bus activity m low power (standby) modes m disable cpu logic (m68000) m freeze control for debugging selected on-chip peripherals m dram refresh controller l cp including: m main controller (risc processor) m three full-duplex serial communication/controllers with the following protocols: n hdlc/sdlc n bisync n uart n ddcmp n totally transparent n v.110 m six serial dma channels dedicated to the three socs m capability to send/receive up to eight buffers/frames without m68000 core intervention m flexible physical interface accessible by sccs for inter-chip digital link (idl), general circuit interface (gci). m pulse code modulation (pcm), and non-multiplexed serial interface (nmsi) operation. m serial communication port (scp) for synchronous communication. m two serial management controllers (smcs) for idl and gci channel. [top] mc68302 parametrics description processor speed (mhz) bus interface (bits) memory voltage (v) package performance file:///h|/imaging/bitting/cpl/20021108_2/11072002_10/moto/11072002_html/mc68302.htm (2 of 12) [11/12/02 2:08:15 pm] mc68302 product summary page integrated multiprotocol processor (imp) 16, 20 32 data no on-chip mmu 5 100 tqfp, 144 tqfp 1.6 (mc68000 core) [top] mc68302 documentation application note id name format size k rev # date last modified order availability an2015/d configuring the chip selects on the mc68302 pdf 62 0 6/17/1991 an2016/d dram control with the mc68302 pdf 266 0 3/21/1991 an2018/d mc68302 getting started with interrupts on the mc68302 pdf 30 0 3/14/1990 an2019/d mc68302 design concept - expanding interrupts on the mc68302 pdf 13 0 7/09/1990 an2020/d mc68302 adapting a wan controller to a lan environment pdf 515 0 1/01/1999 an2021/d mc68302 interfacing the mc68020 to a slave mc68302 pdf 141 0 2/02/1993 an2023/d mc68302 ekb applications - power measurements on the mc68302 pdf 45 1 7/26/1995 an2024/d mc68302 software performance pdf 42 0 6/18/1990 an2026/d mc68302 evaluating edx on the ads302 pdf 167 0 2/27/1991 an2027/d mc68302 using the 302 communications peripheral for powerpc microprocessors pdf 325 0 1/01/1994 an2028/d mc68302 design advisory #1 - mc68sc302 passive isdn protocol engine pdf 5 0 3/31/1997 an2049/d mc68302, mc68360, and mpc860 characteristics and design notes for crystal feedback oscillators pdf 29 0 1/01/1998 brochure id name format size k rev # date last modified order availability 8-16bitpak/d 8-16 bit microcontrollers product portfolio html 1 0 10/15/2002 cfpitchpak/d 68k coldfire product portfolio html 1 0 10/14/2002 data sheets id name format size k rev # date last modified order availability mc68en302/d mc68en302 integrated multiprotocol processor w/ ethernet product brief pdf 55 0 1/01/1995 file:///h|/imaging/bitting/cpl/20021108_2/11072002_10/moto/11072002_html/mc68302.htm (3 of 12) [11/12/02 2:08:15 pm] mc68302 product summary page mc68lc302/d mc68lc302 low cost integrated multiprotocol processor product brief pdf 43 0 1/01/1995 mc68pm302/d mc68pm302 integrated multiprotocol processor w/ pcmcia product brief pdf 636 0 1/01/1995 mc68qh302/d mc68qh302 quad hdlc integrated multiprotocol processor tech. summary product brief pdf 21 0 11/01/1997 mc68sc302p/d mc68sc302 passive isdn protocol engine product brief pdf 46 0 1/01/1996 engineering bulletin id name format size k rev # date last modified order availability eb382/d mc68302fc 132-lead pqfp pdf 31 0 3/30/2001 errata id name format size k rev # date last modified order availability mc68302dec1/d m68302 errata revision c.1 (masks 0f26e, 1f26e) pdf 33 c.1 12/10/1998 - mc68en302dea1/d m68302 device errata - 68en302 integrated multiprotocol processor device pdf 12 a.1 2/20/1997 - mc68en302deb/d m68302 device errata - 68en302 integrated multiprotocol processor with ethernet device pdf 27 b 4/15/1999 - mc68lc302deb/d m68302 device errata - 68lc302 integrated multiprotocol processor devices pdf 7 b 8/02/1996 - mc68lc302dec/d m68302 device errata - mc68lc302 integrated multiprotocol processor devices pdf 27 c 2/09/1999 - mc68pm302deb1/d m68302 device errata - 68pm302 integrated multiprotocol processor devices pdf 11 b.1 10/28/1996 - mc68pm302dec/d m68302 revision c changes - 68pm302 integrated multiprotocol processor devices pdf 6 c 2/27/1997 - mc68qh302dec1/d m68302 device errata - mc68qh302 chip errata pdf 9 c.1 8/05/1998 - mc68sc302dea1/d m68302 device errata - xc68sc302 pdf 6 a.1 2/18/1998 - fact sheets id name format size k rev # date last modified order availability mc68302fact/d m68302 integrated multiprotocol processor pdf 30 0 1/01/1999 file:///h|/imaging/bitting/cpl/20021108_2/11072002_10/moto/11072002_html/mc68302.htm (4 of 12) [11/12/02 2:08:15 pm] mc68302 product summary page miscellaneous id name format size k rev # date last modified order availability m68302fads/d m68302 family application development system pdf 27 0 1/01/1995 mc68302abspec/d mc68302 auto baud support package specifications pdf 60 2 5/01/1994 mc68302deb/d mc68302 deb pdf 9 b 8/06/2001 - mc68302timing/d mc68302 33 mhz ac timing specification pdf 31 - 8/07/2001 - mc68en302sch/d mc68302 schematic for en302 pdf 281 0 2/06/1996 - mc68pm302dec1/d m68302 device errata - 68pm302 integrated multiprotocol processor devices pdf 9 c.1 2/27/1997 - mc68qh302supl/d mc68qh302 supplement to the mc68302 integrated multiprotocol processor user's manual pdf 160 0 10/01/1997 packages & pinouts id name format size k rev # date last modified order availability mc68302.olb mc68302 tqfp part symbol (orcad capture 7.1+) zip 3 0 10/31/1997 - mc68302tqfp mc68302 pin assignment (tqfp) pdf 12 0 12/16/1999 - mc68en302.olb mc68en302 part symbol (orcad capture 7.1+) zip 3 0 11/06/1997 - mc68en302tqfp mc68en302 pin assignment (tqfp) pdf 12 0 12/16/1999 - pbgapres pbga customer tutorial pdf 2947 0 8/17/2000 - product change notices id name format size k rev # date last modified order availability pcn5656/d mc68en302 capacity expansion-pcn5656 pdf 20 - 5/25/2000 - pcn5787/d mc68en302 fab transfer to tsc addendum- pcn5787 pdf 21 - 8/01/2000 - pcn5792/d mc68lc302 fab transfer to tsc-pcn5792 pdf 20 - 8/07/2000 - pcn7917 20x20 lqfp assy move from shc to klm htm 24 0 8/19/2002 - reference manual id name format size k rev # date last modified order availability mc68302um/d mc68302 integrated multiprotocol processor user's manual pdf 1815 3 12/30/1995 - file:///h|/imaging/bitting/cpl/20021108_2/11072002_10/moto/11072002_html/mc68302.htm (5 of 12) [11/12/02 2:08:15 pm] mc68302 product summary page mc68302umad3/d errata to mc68302 integrated multiprotocol processor users manual pdf 80 3 3/19/1992 mc68302umad4/d errata to mc68302 integrated multiprotocol processor users manual pdf 32 4 1/01/1998 mc68302umadd33v/d addendum to mc68302 integrated multiprotocol processor user manual (3.3 v specifications) pdf 191 0.1 7/19/2000 - mc68en302rm/d mc68en302 integrated multiprotocol processor with ethernet reference manual pdf 686 0 1/01/2000 - mc68en302rmad/d errata to mc68en302 integrated multiprotocol processor with ethernet reference manual rev 1 pdf 27 b 11/15/1995 - mc68lc302rm/ad mc68lc302 low power integrated multiprotocol processor reference manual pdf 4958 0 1/01/1995 mc68lc302rmad/d mc68lc302 low power integrated multiprotocol processor reference manual errata pdf 15 1 2/21/1997 - mc68lc302um/d mc68lc302 low power integrated multiprotocol processor reference manual pdf 766 0 8/06/2001 mc68pm302rm/d mc68pm302 integrated multiprotocol processor with pcmcia reference manual pdf 1126 0 1/01/1995 - mc68pm302rmad/d errata to mc68pm302 integrated multiprotocol processor with pcmcia reference manual pdf 25 1 2/11/1997 mc68sc302rm /d mc68sc302 passive isdn protocol engine user's manual pdf 521 0 1/01/1997 - mc68sc302umad/ad mc68sc302 errata to mc68sc302 users manual pdf 30 0 7/15/1998 - reports or presentations id name format size k rev # date last modified order availability ordparts codec, communication processor, and isdn orderable parts pdf 61 - 7/30/2002 - selector guide id name format size k rev # date last modified order availability sg1006/d microcontrollers sps sales guide pdf 600 0 9/26/2002 sg1007/d network and communications processors sales guide pdf 161 0 9/26/2002 sg1011/d software and development tools sales guide pdf 259 1 9/26/2002 file:///h|/imaging/bitting/cpl/20021108_2/11072002_10/moto/11072002_html/mc68302.htm (6 of 12) [11/12/02 2:08:15 pm] mc68302 product summary page users guide id name format size k rev # date last modified order availability mc68302fadsum/d mc68302fads user's manual pdf 863 0 10/17/1995 mc68302piafsum/d mc68302 piafs microcode for mc68302(imp) family user's manual pdf 20 1 1/01/1997 - mc68en302adpum/d mc68en302 adapter user's manual pdf 193 0 1/01/1999 - mc68sc302adsum/d mc68sc302ads application development system user's manual pdf 862 1 1/01/1996 - [top] design tools bsdl files id name vendor id format size k rev # mc68en302bsdl mc68en302 bsdl for jtag logic ver. 0.1 (02/29/1996) motorola txt 20 0.1 drivers id name vendor id format size k rev # mc68302drv01 mc68302 configuration and driver files (12/04/1997) motorola html 1 - microcode id name vendor id format size k rev # mc68302mc1 mc68302 autobaud 2.0 microcode - m68302swaut (02/22/99) motorola zip 5 - mc68302mc2 mc68302 centronics microcode - m68302swcen (02/22/99) motorola zip 1 - mc68302mc3 mc68302 profibus microcode - m68302swpro (02/22/99) motorola zip 1 - mc68302mc4 mc68302 ss7 microcode - m68302swss7 (03/06/2002) motorola zip 104 1.1 mc68302mc5 mc68302 v 110 microcode - m68302swv110 (02/22/99) motorola zip 5 - mc68302mc6 mc68302 piafs microcode - m68302swpia (01/26/00) motorola srx 1 - mc68qh302mc1 autobaud microcode for the mc68qh302 (08/28/98) motorola zip 55 - file:///h|/imaging/bitting/cpl/20021108_2/11072002_10/moto/11072002_html/mc68302.htm (7 of 12) [11/12/02 2:08:15 pm] mc68302 product summary page reference designs id name vendor id format size k rev # mc68qh302rd1 firefly 2b - isdn active terminal adapter reference design using mc68qh302 (preliminary) (01/14/1997) motorola pdf 31 - mc68qh302rd2 firefly 2b - schematics for isdn active terminal adapter reference design using mc68qh302 (preliminary) (01/14/1997) motorola pdf 463 - mc68sc302rd1 mc68sc302 passive isa u-interface reference design bom (01/16/1997) motorola txt 6 - mc68sc302rd2 mc68sc302 passive isdn terminal adapter design (gerber) (06/27/1997) motorola zip 109 - mc68sc302rd3 mc68sc302 passive isdn terminal adapter design (tango pro cad) (01/07/1997) motorola zip 288 - mc68sc302rd4 mc68sc302 passive u isdn card reference design (12/06/1996) motorola pdf 546 - mc68sc302rd5 mc68sc302 pnp eeprom maker script and example files (for sun in perl) (01/08/1997) motorola tar 160 - mc68sc302rd6 mc68sc302 s/t-interface passive terminal adapter reference design (01/08/1997) motorola pdf 282 - schematics id name vendor id format size k rev # m68en302fadssch m68en302 fads adapter (ena) schematics (02/06/1996) motorola pdf 281 - m68xx302fadssch m68xx302 fads schematics (12/04/1996) motorola pdf 630 - software id name vendor id format size k rev # m68xx302fadssw1 m68xx302 family application development system (302 fads) software (12/23/1997) motorola zip 563 0.4 mc68302adssw1 mc68302 application development system software (12/04/1996) motorola html 0 - mc68302adssw2 mc68302ads ibm-pc host files (12/04/1996) motorola html 0 - mc68302cod1 mc68302 code for setting up an scc in uart mode (12/04/1996) motorola txt 8 - mc68302cod2 mc68302 demo code for the 302ads board 08/31/1990 motorola html 1 - file:///h|/imaging/bitting/cpl/20021108_2/11072002_10/moto/11072002_html/mc68302.htm (8 of 12) [11/12/02 2:08:15 pm] mc68302 product summary page mc68302cod3 sample code - configuring a uart on the mc68302 (12/04/1996) motorola txt 1 - mc68302cod4 mc68302 source code for isdn smart nt1 layer 1 (02/04/1997) motorola zip 6 - mc68302cod5 mc68302 confidence test software (10/22/2001) motorola zip 194 - mc68en302cod1 mc68en302 software example (05/13/1997) motorola zip 454 - mc68sc302sw mc68sc302 application development system software ** not recommended for new design. part is on eol notification. ** (09/24/1997) motorola zip 271 3.1 supporting information id name vendor id format size k rev # mc68en302_start mc68en302 getting started hints motorola txt 8 - [top] orderable parts information partnumber package info life cycle description (code) remarks budgetary price qty 1000+ ($us) order availability mc68302cfc16c pqfp 132 0.950*.950p.025 product maturity/saturation(4) 16mhz, extended temp $16.04 mc68302cfc20c pqfp 132 0.950*.950p.025 product maturity/saturation(4) 20mhz, extended temp $18.20 mc68302cpv16vc lqfp 144 20*20*1.4p0.5 product maturity/saturation(4) 16mhz, extended temp $19.37 mc68302crc16c pga 132 product maturity/saturation(4) 16mhz, extended temp $42.44 mc68302crc20c pga 132 product maturity/saturation(4) 20mhz, extended temp $53.05 mc68302fc16c pqfp 132 0.950*.950p.025 product maturity/saturation(4) 16mhz $13.35 file:///h|/imaging/bitting/cpl/20021108_2/11072002_10/moto/11072002_html/mc68302.htm (9 of 12) [11/12/02 2:08:15 pm] mc68302 product summary page mc68302fc16cr2 pqfp 132 0.950*.950p.025 product maturity/saturation(4) packaged in tape & reel $15.72 - mc68302fc20c pqfp 132 0.950*.950p.025 product maturity/saturation(4) 20mhz $15.17 mc68302fc20cr2 pqfp 132 0.950*.950p.025 product maturity/saturation(4) packaged in tape & reel - - mc68302fc25c pqfp 132 0.950*.950p.025 product maturity/saturation(4) 25mhz $16.97 mc68302fc25cr2 pqfp 132 0.950*.950p.025 product maturity/saturation(4) packaged in tape & reel $20.44 mc68302pv16c lqfp 144 20*20*1.4p0.5 product maturity/saturation(4) 16mhz $12.91 mc68302pv16vc lqfp 144 20*20*1.4p0.5 product maturity/saturation(4) 16mhz $16.13 mc68302pv20c lqfp 144 20*20*1.4p0.5 product maturity/saturation(4) 20mhz $14.71 mc68302pv25c lqfp 144 20*20*1.4p0.5 product maturity/saturation(4) 25mhz $16.52 mc68302pv33c lqfp 144 20*20*1.4p0.5 product maturity/saturation(4) 33mhz $18.32 mc68302rc16c pga 132 product maturity/saturation(4) 16mhz $40.32 mc68302rc20c pga 132 product maturity/saturation(4) 20mhz $50.40 mc68302rc25c pga 132 product maturity/saturation(4) 25mhz $63.00 spak302cfc20c pqfp 132 0.950*.950p.025 product maturity/saturation(4) part number for ordering samples only $20.19 spak302fc25c pqfp 132 0.950*.950p.025 product maturity/saturation(4) part number for ordering samples only $20.44 spak302pv16vc lqfp 144 20*20*1.4p0.5 product maturity/saturation(4) part number for ordering samples only $20.47 file:///h|/imaging/bitting/cpl/20021108_2/11072002_10/moto/11072002_html/mc68302.htm (10 of 12) [11/12/02 2:08:15 pm] mc68302 product summary page spak302pv33c lqfp 144 20*20*1.4p0.5 product maturity/saturation(4) part number for ordering samples only $21.79 spak302rc25c pga 132 product maturity/saturation(4) part number for ordering samples only $50.79 kMC68LC302PU16CT lqfp 100 14*14*1.4p0.5 product maturity/saturation(4) part number for ordering samples only $11.35 kmc68lc302pu20ct lqfp 100 14*14*1.4p0.5 product maturity/saturation(4) part number for ordering samples only $13.61 kmc68lc302pu25ct lqfp 100 14*14*1.4p0.5 product maturity/saturation(4) part number for ordering samples only $15.87 km68lc302pu20vct lqfp 100 14*14*1.4p0.5 product maturity/saturation(4) part number for ordering samples only $15.87 kmc68en302pv20bt lqfp 144 20*20*1.4p0.5 product maturity/saturation(4) part number for ordering samples only $22.73 kmc68en302pv25bt lqfp 144 20*20*1.4p0.5 product maturity/saturation(4) part number for ordering samples only $27.27 mc68en302cpv20bt lqfp 144 20*20*1.4p0.5 product maturity/saturation(4) 20mhz $21.65 mc68en302pv20bt lqfp 144 20*20*1.4p0.5 product maturity/saturation(4) 20mhz $18.04 mc68en302pv25bt lqfp 144 20*20*1.4p0.5 product maturity/saturation(4) 25mhz $21.65 m68lc302cpu16vct lqfp 100 14*14*1.4p0.5 product maturity/saturation(4) - $13.05 file:///h|/imaging/bitting/cpl/20021108_2/11072002_10/moto/11072002_html/mc68302.htm (11 of 12) [11/12/02 2:08:15 pm] mc68302 product summary page m68lc302cpu20vct lqfp 100 14*14*1.4p0.5 product maturity/saturation(4) - $13.44 mc68lc302cpu16ct lqfp 100 14*14*1.4p0.5 product maturity/saturation(4) 16mhz $8.74 mc68lc302cpu20ct lqfp 100 14*14*1.4p0.5 product maturity/saturation(4) 20mhz $10.93 MC68LC302PU16CT lqfp 100 14*14*1.4p0.5 product maturity/saturation(4) 16mhz $8.56 mc68lc302pu16vct lqfp 100 14*14*1.4p0.5 product maturity/saturation(4) 16mhz $12.80 mc68lc302pu20ct lqfp 100 14*14*1.4p0.5 product maturity/saturation(4) 20mhz $10.71 mc68lc302pu20vct lqfp 100 14*14*1.4p0.5 product maturity/saturation(4) 20mhz $13.18 mc68lc302pu25ct lqfp 100 14*14*1.4p0.5 product maturity/saturation(4) 25mhz $12.80 [top] motorola home | semiconductors | login | support | contact us | site map products | documentation | tools | design resources | applications file:///h|/imaging/bitting/cpl/20021108_2/11072002_10/moto/11072002_html/mc68302.htm (12 of 12) [11/12/02 2:08:15 pm] |
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